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i40e: support for suspend and resume
Add basic support for handling suspend and resume. We'll add Wake-on-LAN support later. Change-Id: Iea5e11c81bd9289a5bdbf086de8f626911a0b5ce Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -133,6 +133,7 @@ enum i40e_state_t {
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__I40E_GLOBAL_RESET_REQUESTED,
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__I40E_GLOBAL_RESET_REQUESTED,
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__I40E_EMP_RESET_REQUESTED,
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__I40E_EMP_RESET_REQUESTED,
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__I40E_FILTER_OVERFLOW_PROMISC,
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__I40E_FILTER_OVERFLOW_PROMISC,
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__I40E_SUSPENDED,
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};
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};
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enum i40e_interrupt_policy {
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enum i40e_interrupt_policy {
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@ -7749,7 +7749,11 @@ static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
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dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
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dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
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/* shutdown all operations */
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/* shutdown all operations */
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i40e_pf_quiesce_all_vsi(pf);
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if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
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rtnl_lock();
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i40e_prep_for_reset(pf);
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rtnl_unlock();
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}
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/* Request a slot reset */
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/* Request a slot reset */
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return PCI_ERS_RESULT_NEED_RESET;
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return PCI_ERS_RESULT_NEED_RESET;
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@ -7812,9 +7816,95 @@ static void i40e_pci_error_resume(struct pci_dev *pdev)
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struct i40e_pf *pf = pci_get_drvdata(pdev);
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struct i40e_pf *pf = pci_get_drvdata(pdev);
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dev_info(&pdev->dev, "%s\n", __func__);
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dev_info(&pdev->dev, "%s\n", __func__);
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if (test_bit(__I40E_SUSPENDED, &pf->state))
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return;
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rtnl_lock();
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i40e_handle_reset_warning(pf);
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i40e_handle_reset_warning(pf);
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rtnl_lock();
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}
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}
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/**
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* i40e_shutdown - PCI callback for shutting down
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* @pdev: PCI device information struct
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**/
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static void i40e_shutdown(struct pci_dev *pdev)
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{
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struct i40e_pf *pf = pci_get_drvdata(pdev);
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set_bit(__I40E_SUSPENDED, &pf->state);
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set_bit(__I40E_DOWN, &pf->state);
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rtnl_lock();
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i40e_prep_for_reset(pf);
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rtnl_unlock();
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if (system_state == SYSTEM_POWER_OFF) {
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pci_wake_from_d3(pdev, false); /* No WoL support yet */
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pci_set_power_state(pdev, PCI_D3hot);
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}
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}
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#ifdef CONFIG_PM
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/**
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* i40e_suspend - PCI callback for moving to D3
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* @pdev: PCI device information struct
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**/
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static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct i40e_pf *pf = pci_get_drvdata(pdev);
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set_bit(__I40E_SUSPENDED, &pf->state);
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set_bit(__I40E_DOWN, &pf->state);
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rtnl_lock();
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i40e_prep_for_reset(pf);
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rtnl_unlock();
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pci_wake_from_d3(pdev, false); /* No WoL support yet */
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pci_set_power_state(pdev, PCI_D3hot);
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return 0;
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}
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/**
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* i40e_resume - PCI callback for waking up from D3
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* @pdev: PCI device information struct
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**/
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static int i40e_resume(struct pci_dev *pdev)
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{
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struct i40e_pf *pf = pci_get_drvdata(pdev);
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u32 err;
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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/* pci_restore_state() clears dev->state_saves, so
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* call pci_save_state() again to restore it.
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*/
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pci_save_state(pdev);
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err = pci_enable_device_mem(pdev);
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if (err) {
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dev_err(&pdev->dev,
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"%s: Cannot enable PCI device from suspend\n",
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__func__);
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return err;
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}
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pci_set_master(pdev);
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/* no wakeup events while running */
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pci_wake_from_d3(pdev, false);
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/* handling the reset will rebuild the device state */
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if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
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clear_bit(__I40E_DOWN, &pf->state);
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rtnl_lock();
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i40e_reset_and_rebuild(pf, false);
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rtnl_unlock();
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}
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return 0;
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}
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#endif
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static const struct pci_error_handlers i40e_err_handler = {
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static const struct pci_error_handlers i40e_err_handler = {
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.error_detected = i40e_pci_error_detected,
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.error_detected = i40e_pci_error_detected,
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.slot_reset = i40e_pci_error_slot_reset,
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.slot_reset = i40e_pci_error_slot_reset,
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@ -7826,6 +7916,11 @@ static struct pci_driver i40e_driver = {
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.id_table = i40e_pci_tbl,
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.id_table = i40e_pci_tbl,
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.probe = i40e_probe,
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.probe = i40e_probe,
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.remove = i40e_remove,
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.remove = i40e_remove,
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#ifdef CONFIG_PM
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.suspend = i40e_suspend,
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.resume = i40e_resume,
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#endif
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.shutdown = i40e_shutdown,
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.err_handler = &i40e_err_handler,
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.err_handler = &i40e_err_handler,
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.sriov_configure = i40e_pci_sriov_configure,
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.sriov_configure = i40e_pci_sriov_configure,
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};
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};
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