mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-16 01:04:08 +08:00
Merge 3.6-rc7 into driver-core-next
This pulls in the fixes in that branch that are needed here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
commit
8f949b9a7e
@ -210,3 +210,15 @@ Users:
|
||||
firmware assigned instance number of the PCI
|
||||
device that can help in understanding the firmware
|
||||
intended order of the PCI device.
|
||||
|
||||
What: /sys/bus/pci/devices/.../d3cold_allowed
|
||||
Date: July 2012
|
||||
Contact: Huang Ying <ying.huang@intel.com>
|
||||
Description:
|
||||
d3cold_allowed is bit to control whether the corresponding PCI
|
||||
device can be put into D3Cold state. If it is cleared, the
|
||||
device will never be put into D3Cold state. If it is set, the
|
||||
device may be put into D3Cold state if other requirements are
|
||||
satisfied too. Reading this attribute will show the current
|
||||
value of d3cold_allowed bit. Writing this attribute will set
|
||||
the value of d3cold_allowed bit.
|
||||
|
@ -3,15 +3,21 @@
|
||||
biodoc.txt
|
||||
- Notes on the Generic Block Layer Rewrite in Linux 2.5
|
||||
capability.txt
|
||||
- Generic Block Device Capability (/sys/block/<disk>/capability)
|
||||
- Generic Block Device Capability (/sys/block/<device>/capability)
|
||||
cfq-iosched.txt
|
||||
- CFQ IO scheduler tunables
|
||||
data-integrity.txt
|
||||
- Block data integrity
|
||||
deadline-iosched.txt
|
||||
- Deadline IO scheduler tunables
|
||||
ioprio.txt
|
||||
- Block io priorities (in CFQ scheduler)
|
||||
queue-sysfs.txt
|
||||
- Queue's sysfs entries
|
||||
request.txt
|
||||
- The members of struct request (in include/linux/blkdev.h)
|
||||
stat.txt
|
||||
- Block layer statistics in /sys/block/<dev>/stat
|
||||
- Block layer statistics in /sys/block/<device>/stat
|
||||
switching-sched.txt
|
||||
- Switching I/O schedulers at runtime
|
||||
writeback_cache_control.txt
|
||||
|
@ -1,3 +1,14 @@
|
||||
CFQ (Complete Fairness Queueing)
|
||||
===============================
|
||||
|
||||
The main aim of CFQ scheduler is to provide a fair allocation of the disk
|
||||
I/O bandwidth for all the processes which requests an I/O operation.
|
||||
|
||||
CFQ maintains the per process queue for the processes which request I/O
|
||||
operation(syncronous requests). In case of asynchronous requests, all the
|
||||
requests from all the processes are batched together according to their
|
||||
process's I/O priority.
|
||||
|
||||
CFQ ioscheduler tunables
|
||||
========================
|
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|
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@ -25,6 +36,72 @@ there are multiple spindles behind single LUN (Host based hardware RAID
|
||||
controller or for storage arrays), setting slice_idle=0 might end up in better
|
||||
throughput and acceptable latencies.
|
||||
|
||||
back_seek_max
|
||||
-------------
|
||||
This specifies, given in Kbytes, the maximum "distance" for backward seeking.
|
||||
The distance is the amount of space from the current head location to the
|
||||
sectors that are backward in terms of distance.
|
||||
|
||||
This parameter allows the scheduler to anticipate requests in the "backward"
|
||||
direction and consider them as being the "next" if they are within this
|
||||
distance from the current head location.
|
||||
|
||||
back_seek_penalty
|
||||
-----------------
|
||||
This parameter is used to compute the cost of backward seeking. If the
|
||||
backward distance of request is just 1/back_seek_penalty from a "front"
|
||||
request, then the seeking cost of two requests is considered equivalent.
|
||||
|
||||
So scheduler will not bias toward one or the other request (otherwise scheduler
|
||||
will bias toward front request). Default value of back_seek_penalty is 2.
|
||||
|
||||
fifo_expire_async
|
||||
-----------------
|
||||
This parameter is used to set the timeout of asynchronous requests. Default
|
||||
value of this is 248ms.
|
||||
|
||||
fifo_expire_sync
|
||||
----------------
|
||||
This parameter is used to set the timeout of synchronous requests. Default
|
||||
value of this is 124ms. In case to favor synchronous requests over asynchronous
|
||||
one, this value should be decreased relative to fifo_expire_async.
|
||||
|
||||
slice_async
|
||||
-----------
|
||||
This parameter is same as of slice_sync but for asynchronous queue. The
|
||||
default value is 40ms.
|
||||
|
||||
slice_async_rq
|
||||
--------------
|
||||
This parameter is used to limit the dispatching of asynchronous request to
|
||||
device request queue in queue's slice time. The maximum number of request that
|
||||
are allowed to be dispatched also depends upon the io priority. Default value
|
||||
for this is 2.
|
||||
|
||||
slice_sync
|
||||
----------
|
||||
When a queue is selected for execution, the queues IO requests are only
|
||||
executed for a certain amount of time(time_slice) before switching to another
|
||||
queue. This parameter is used to calculate the time slice of synchronous
|
||||
queue.
|
||||
|
||||
time_slice is computed using the below equation:-
|
||||
time_slice = slice_sync + (slice_sync/5 * (4 - prio)). To increase the
|
||||
time_slice of synchronous queue, increase the value of slice_sync. Default
|
||||
value is 100ms.
|
||||
|
||||
quantum
|
||||
-------
|
||||
This specifies the number of request dispatched to the device queue. In a
|
||||
queue's time slice, a request will not be dispatched if the number of request
|
||||
in the device exceeds this parameter. This parameter is used for synchronous
|
||||
request.
|
||||
|
||||
In case of storage with several disk, this setting can limit the parallel
|
||||
processing of request. Therefore, increasing the value can imporve the
|
||||
performace although this can cause the latency of some I/O to increase due
|
||||
to more number of requests.
|
||||
|
||||
CFQ IOPS Mode for group scheduling
|
||||
===================================
|
||||
Basic CFQ design is to provide priority based time slices. Higher priority
|
||||
|
@ -9,20 +9,71 @@ These files are the ones found in the /sys/block/xxx/queue/ directory.
|
||||
Files denoted with a RO postfix are readonly and the RW postfix means
|
||||
read-write.
|
||||
|
||||
add_random (RW)
|
||||
----------------
|
||||
This file allows to trun off the disk entropy contribution. Default
|
||||
value of this file is '1'(on).
|
||||
|
||||
discard_granularity (RO)
|
||||
-----------------------
|
||||
This shows the size of internal allocation of the device in bytes, if
|
||||
reported by the device. A value of '0' means device does not support
|
||||
the discard functionality.
|
||||
|
||||
discard_max_bytes (RO)
|
||||
----------------------
|
||||
Devices that support discard functionality may have internal limits on
|
||||
the number of bytes that can be trimmed or unmapped in a single operation.
|
||||
The discard_max_bytes parameter is set by the device driver to the maximum
|
||||
number of bytes that can be discarded in a single operation. Discard
|
||||
requests issued to the device must not exceed this limit. A discard_max_bytes
|
||||
value of 0 means that the device does not support discard functionality.
|
||||
|
||||
discard_zeroes_data (RO)
|
||||
------------------------
|
||||
When read, this file will show if the discarded block are zeroed by the
|
||||
device or not. If its value is '1' the blocks are zeroed otherwise not.
|
||||
|
||||
hw_sector_size (RO)
|
||||
-------------------
|
||||
This is the hardware sector size of the device, in bytes.
|
||||
|
||||
iostats (RW)
|
||||
-------------
|
||||
This file is used to control (on/off) the iostats accounting of the
|
||||
disk.
|
||||
|
||||
logical_block_size (RO)
|
||||
-----------------------
|
||||
This is the logcal block size of the device, in bytes.
|
||||
|
||||
max_hw_sectors_kb (RO)
|
||||
----------------------
|
||||
This is the maximum number of kilobytes supported in a single data transfer.
|
||||
|
||||
max_integrity_segments (RO)
|
||||
---------------------------
|
||||
When read, this file shows the max limit of integrity segments as
|
||||
set by block layer which a hardware controller can handle.
|
||||
|
||||
max_sectors_kb (RW)
|
||||
-------------------
|
||||
This is the maximum number of kilobytes that the block layer will allow
|
||||
for a filesystem request. Must be smaller than or equal to the maximum
|
||||
size allowed by the hardware.
|
||||
|
||||
max_segments (RO)
|
||||
-----------------
|
||||
Maximum number of segments of the device.
|
||||
|
||||
max_segment_size (RO)
|
||||
---------------------
|
||||
Maximum segment size of the device.
|
||||
|
||||
minimum_io_size (RO)
|
||||
--------------------
|
||||
This is the smallest preferred io size reported by the device.
|
||||
|
||||
nomerges (RW)
|
||||
-------------
|
||||
This enables the user to disable the lookup logic involved with IO
|
||||
@ -45,11 +96,24 @@ per-block-cgroup request pool. IOW, if there are N block cgroups,
|
||||
each request queue may have upto N request pools, each independently
|
||||
regulated by nr_requests.
|
||||
|
||||
optimal_io_size (RO)
|
||||
--------------------
|
||||
This is the optimal io size reported by the device.
|
||||
|
||||
physical_block_size (RO)
|
||||
------------------------
|
||||
This is the physical block size of device, in bytes.
|
||||
|
||||
read_ahead_kb (RW)
|
||||
------------------
|
||||
Maximum number of kilobytes to read-ahead for filesystems on this block
|
||||
device.
|
||||
|
||||
rotational (RW)
|
||||
---------------
|
||||
This file is used to stat if the device is of rotational type or
|
||||
non-rotational type.
|
||||
|
||||
rq_affinity (RW)
|
||||
----------------
|
||||
If this option is '1', the block layer will migrate request completions to the
|
||||
|
@ -10,8 +10,8 @@ Required properties:
|
||||
- compatible : Should be "fsl,<chip>-esdhc"
|
||||
|
||||
Optional properties:
|
||||
- fsl,cd-internal : Indicate to use controller internal card detection
|
||||
- fsl,wp-internal : Indicate to use controller internal write protection
|
||||
- fsl,cd-controller : Indicate to use controller internal card detection
|
||||
- fsl,wp-controller : Indicate to use controller internal write protection
|
||||
|
||||
Examples:
|
||||
|
||||
@ -19,8 +19,8 @@ esdhc@70004000 {
|
||||
compatible = "fsl,imx51-esdhc";
|
||||
reg = <0x70004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
fsl,cd-internal;
|
||||
fsl,wp-internal;
|
||||
fsl,cd-controller;
|
||||
fsl,wp-controller;
|
||||
};
|
||||
|
||||
esdhc@70008000 {
|
||||
|
@ -579,7 +579,7 @@ Why: KVM tracepoints provide mostly equivalent information in a much more
|
||||
----------------------------
|
||||
|
||||
What: at91-mci driver ("CONFIG_MMC_AT91")
|
||||
When: 3.7
|
||||
When: 3.8
|
||||
Why: There are two mci drivers: at91-mci and atmel-mci. The PDC support
|
||||
was added to atmel-mci as a first step to support more chips.
|
||||
Then at91-mci was kept only for old IP versions (on at91rm9200 and
|
||||
|
@ -21,6 +21,7 @@ Supported adapters:
|
||||
* Intel DH89xxCC (PCH)
|
||||
* Intel Panther Point (PCH)
|
||||
* Intel Lynx Point (PCH)
|
||||
* Intel Lynx Point-LP (PCH)
|
||||
Datasheets: Publicly available at the Intel website
|
||||
|
||||
On Intel Patsburg and later chipsets, both the normal host SMBus controller
|
||||
|
@ -31,7 +31,7 @@ static void keep_alive(void)
|
||||
* or "-e" to enable the card.
|
||||
*/
|
||||
|
||||
void term(int sig)
|
||||
static void term(int sig)
|
||||
{
|
||||
close(fd);
|
||||
fprintf(stderr, "Stopping watchdog ticks...\n");
|
||||
|
@ -3390,7 +3390,7 @@ M: "Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
W: http://i2c.wiki.kernel.org/
|
||||
T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-i2c/
|
||||
T: git git://git.fluff.org/bjdooks/linux.git
|
||||
T: git git://git.pengutronix.de/git/wsa/linux.git
|
||||
S: Maintained
|
||||
F: Documentation/i2c/
|
||||
F: drivers/i2c/
|
||||
|
2
Makefile
2
Makefile
@ -1,7 +1,7 @@
|
||||
VERSION = 3
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc3
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
@ -6,7 +6,7 @@ config ARM
|
||||
select HAVE_DMA_API_DEBUG
|
||||
select HAVE_IDE if PCI || ISA || PCMCIA
|
||||
select HAVE_DMA_ATTRS
|
||||
select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
|
||||
select HAVE_DMA_CONTIGUOUS if MMU
|
||||
select HAVE_MEMBLOCK
|
||||
select RTC_LIB
|
||||
select SYS_SUPPORTS_APM_EMULATION
|
||||
@ -2144,6 +2144,7 @@ source "drivers/cpufreq/Kconfig"
|
||||
config CPU_FREQ_IMX
|
||||
tristate "CPUfreq driver for i.MX CPUs"
|
||||
depends on ARCH_MXC && CPU_FREQ
|
||||
select CPU_FREQ_TABLE
|
||||
help
|
||||
This enables the CPUfreq driver for i.MX CPUs.
|
||||
|
||||
|
@ -356,15 +356,15 @@ choice
|
||||
is nothing connected to read from the DCC.
|
||||
|
||||
config DEBUG_SEMIHOSTING
|
||||
bool "Kernel low-level debug output via semihosting I"
|
||||
bool "Kernel low-level debug output via semihosting I/O"
|
||||
help
|
||||
Semihosting enables code running on an ARM target to use
|
||||
the I/O facilities on a host debugger/emulator through a
|
||||
simple SVC calls. The host debugger or emulator must have
|
||||
simple SVC call. The host debugger or emulator must have
|
||||
semihosting enabled for the special svc call to be trapped
|
||||
otherwise the kernel will crash.
|
||||
|
||||
This is known to work with OpenOCD, as wellas
|
||||
This is known to work with OpenOCD, as well as
|
||||
ARM's Fast Models, or any other controlling environment
|
||||
that implements semihosting.
|
||||
|
||||
|
@ -284,10 +284,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
|
||||
zinstall uinstall install: vmlinux
|
||||
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
|
||||
|
||||
%.dtb:
|
||||
%.dtb: scripts
|
||||
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
|
||||
|
||||
dtbs:
|
||||
dtbs: scripts
|
||||
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
|
||||
|
||||
# We use MRPROPER_FILES and CLEAN_FILES now
|
||||
|
@ -659,10 +659,14 @@ __armv7_mmu_cache_on:
|
||||
#ifdef CONFIG_CPU_ENDIAN_BE8
|
||||
orr r0, r0, #1 << 25 @ big-endian page tables
|
||||
#endif
|
||||
mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
|
||||
orrne r0, r0, #1 @ MMU enabled
|
||||
movne r1, #0xfffffffd @ domain 0 = client
|
||||
bic r6, r6, #1 << 31 @ 32-bit translation system
|
||||
bic r6, r6, #3 << 0 @ use only ttbr0
|
||||
mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
|
||||
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
|
||||
mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
|
||||
#endif
|
||||
mcr p15, 0, r0, c7, c5, 4 @ ISB
|
||||
mcr p15, 0, r0, c1, c0, 0 @ load control register
|
||||
|
@ -154,5 +154,10 @@
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c3";
|
||||
};
|
||||
|
||||
wdt2: wdt@44e35000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -15,7 +15,7 @@
|
||||
compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
|
||||
|
||||
chosen {
|
||||
bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
|
||||
};
|
||||
|
||||
ahb {
|
||||
|
@ -25,8 +25,8 @@
|
||||
aips@70000000 { /* aips-1 */
|
||||
spba@70000000 {
|
||||
esdhc@70004000 { /* ESDHC1 */
|
||||
fsl,cd-internal;
|
||||
fsl,wp-internal;
|
||||
fsl,cd-controller;
|
||||
fsl,wp-controller;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -41,9 +41,13 @@
|
||||
};
|
||||
power-blue {
|
||||
label = "power:blue";
|
||||
gpios = <&gpio1 11 0>;
|
||||
gpios = <&gpio1 10 0>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
power-red {
|
||||
label = "power:red";
|
||||
gpios = <&gpio1 11 0>;
|
||||
};
|
||||
usb1 {
|
||||
label = "usb1:blue";
|
||||
gpios = <&gpio1 12 0>;
|
||||
|
@ -66,6 +66,7 @@
|
||||
|
||||
vcxio: regulator@8 {
|
||||
compatible = "ti,twl6030-vcxio";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vusb: regulator@9 {
|
||||
@ -74,10 +75,12 @@
|
||||
|
||||
v1v8: regulator@10 {
|
||||
compatible = "ti,twl6030-v1v8";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2v1: regulator@11 {
|
||||
compatible = "ti,twl6030-v2v1";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
clk32kg: regulator@12 {
|
||||
|
@ -33,7 +33,7 @@ CONFIG_AEABI=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=13
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"
|
||||
CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"
|
||||
CONFIG_CMDLINE_FORCE=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_VFP=y
|
||||
|
@ -86,6 +86,7 @@ CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_LM3530=y
|
||||
CONFIG_LEDS_LP5521=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_AB8500=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
|
@ -320,4 +320,12 @@
|
||||
.size \name , . - \name
|
||||
.endm
|
||||
|
||||
.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
|
||||
#ifndef CONFIG_CPU_USE_DOMAINS
|
||||
adds \tmp, \addr, #\size - 1
|
||||
sbcccs \tmp, \tmp, \limit
|
||||
bcs \bad
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#endif /* __ASM_ASSEMBLER_H__ */
|
||||
|
@ -202,6 +202,13 @@ static inline void dma_free_writecombine(struct device *dev, size_t size,
|
||||
return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
|
||||
}
|
||||
|
||||
/*
|
||||
* This can be called during early boot to increase the size of the atomic
|
||||
* coherent DMA pool above the default value of 256KiB. It must be called
|
||||
* before postcore_initcall.
|
||||
*/
|
||||
extern void __init init_dma_coherent_pool_size(unsigned long size);
|
||||
|
||||
/*
|
||||
* This can be called during boot to increase the size of the consistent
|
||||
* DMA region above it's default value of 2MB. It must be called before the
|
||||
|
@ -187,6 +187,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
|
||||
#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET)
|
||||
#endif
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#ifndef PHYS_OFFSET
|
||||
#ifdef PLAT_PHYS_OFFSET
|
||||
@ -196,6 +197,8 @@ static inline unsigned long __phys_to_virt(unsigned long x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* PFNs are used to describe any physical page; this means
|
||||
* PFN 0 == physical address 0.
|
||||
|
@ -199,6 +199,9 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
|
||||
{
|
||||
pgtable_page_dtor(pte);
|
||||
|
||||
#ifdef CONFIG_ARM_LPAE
|
||||
tlb_add_flush(tlb, addr);
|
||||
#else
|
||||
/*
|
||||
* With the classic ARM MMU, a pte page has two corresponding pmd
|
||||
* entries, each covering 1MB.
|
||||
@ -206,6 +209,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
|
||||
addr &= PMD_MASK;
|
||||
tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
|
||||
tlb_add_flush(tlb, addr + SZ_1M);
|
||||
#endif
|
||||
|
||||
tlb_remove_page(tlb, pte);
|
||||
}
|
||||
|
@ -101,28 +101,39 @@ extern int __get_user_1(void *);
|
||||
extern int __get_user_2(void *);
|
||||
extern int __get_user_4(void *);
|
||||
|
||||
#define __get_user_x(__r2,__p,__e,__s,__i...) \
|
||||
#define __GUP_CLOBBER_1 "lr", "cc"
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
#define __GUP_CLOBBER_2 "ip", "lr", "cc"
|
||||
#else
|
||||
#define __GUP_CLOBBER_2 "lr", "cc"
|
||||
#endif
|
||||
#define __GUP_CLOBBER_4 "lr", "cc"
|
||||
|
||||
#define __get_user_x(__r2,__p,__e,__l,__s) \
|
||||
__asm__ __volatile__ ( \
|
||||
__asmeq("%0", "r0") __asmeq("%1", "r2") \
|
||||
__asmeq("%3", "r1") \
|
||||
"bl __get_user_" #__s \
|
||||
: "=&r" (__e), "=r" (__r2) \
|
||||
: "0" (__p) \
|
||||
: __i, "cc")
|
||||
: "0" (__p), "r" (__l) \
|
||||
: __GUP_CLOBBER_##__s)
|
||||
|
||||
#define get_user(x,p) \
|
||||
#define __get_user_check(x,p) \
|
||||
({ \
|
||||
unsigned long __limit = current_thread_info()->addr_limit - 1; \
|
||||
register const typeof(*(p)) __user *__p asm("r0") = (p);\
|
||||
register unsigned long __r2 asm("r2"); \
|
||||
register unsigned long __l asm("r1") = __limit; \
|
||||
register int __e asm("r0"); \
|
||||
switch (sizeof(*(__p))) { \
|
||||
case 1: \
|
||||
__get_user_x(__r2, __p, __e, 1, "lr"); \
|
||||
break; \
|
||||
__get_user_x(__r2, __p, __e, __l, 1); \
|
||||
break; \
|
||||
case 2: \
|
||||
__get_user_x(__r2, __p, __e, 2, "r3", "lr"); \
|
||||
__get_user_x(__r2, __p, __e, __l, 2); \
|
||||
break; \
|
||||
case 4: \
|
||||
__get_user_x(__r2, __p, __e, 4, "lr"); \
|
||||
__get_user_x(__r2, __p, __e, __l, 4); \
|
||||
break; \
|
||||
default: __e = __get_user_bad(); break; \
|
||||
} \
|
||||
@ -130,42 +141,57 @@ extern int __get_user_4(void *);
|
||||
__e; \
|
||||
})
|
||||
|
||||
#define get_user(x,p) \
|
||||
({ \
|
||||
might_fault(); \
|
||||
__get_user_check(x,p); \
|
||||
})
|
||||
|
||||
extern int __put_user_1(void *, unsigned int);
|
||||
extern int __put_user_2(void *, unsigned int);
|
||||
extern int __put_user_4(void *, unsigned int);
|
||||
extern int __put_user_8(void *, unsigned long long);
|
||||
|
||||
#define __put_user_x(__r2,__p,__e,__s) \
|
||||
#define __put_user_x(__r2,__p,__e,__l,__s) \
|
||||
__asm__ __volatile__ ( \
|
||||
__asmeq("%0", "r0") __asmeq("%2", "r2") \
|
||||
__asmeq("%3", "r1") \
|
||||
"bl __put_user_" #__s \
|
||||
: "=&r" (__e) \
|
||||
: "0" (__p), "r" (__r2) \
|
||||
: "0" (__p), "r" (__r2), "r" (__l) \
|
||||
: "ip", "lr", "cc")
|
||||
|
||||
#define put_user(x,p) \
|
||||
#define __put_user_check(x,p) \
|
||||
({ \
|
||||
unsigned long __limit = current_thread_info()->addr_limit - 1; \
|
||||
register const typeof(*(p)) __r2 asm("r2") = (x); \
|
||||
register const typeof(*(p)) __user *__p asm("r0") = (p);\
|
||||
register unsigned long __l asm("r1") = __limit; \
|
||||
register int __e asm("r0"); \
|
||||
switch (sizeof(*(__p))) { \
|
||||
case 1: \
|
||||
__put_user_x(__r2, __p, __e, 1); \
|
||||
__put_user_x(__r2, __p, __e, __l, 1); \
|
||||
break; \
|
||||
case 2: \
|
||||
__put_user_x(__r2, __p, __e, 2); \
|
||||
__put_user_x(__r2, __p, __e, __l, 2); \
|
||||
break; \
|
||||
case 4: \
|
||||
__put_user_x(__r2, __p, __e, 4); \
|
||||
__put_user_x(__r2, __p, __e, __l, 4); \
|
||||
break; \
|
||||
case 8: \
|
||||
__put_user_x(__r2, __p, __e, 8); \
|
||||
__put_user_x(__r2, __p, __e, __l, 8); \
|
||||
break; \
|
||||
default: __e = __put_user_bad(); break; \
|
||||
} \
|
||||
__e; \
|
||||
})
|
||||
|
||||
#define put_user(x,p) \
|
||||
({ \
|
||||
might_fault(); \
|
||||
__put_user_check(x,p); \
|
||||
})
|
||||
|
||||
#else /* CONFIG_MMU */
|
||||
|
||||
/*
|
||||
@ -219,6 +245,7 @@ do { \
|
||||
unsigned long __gu_addr = (unsigned long)(ptr); \
|
||||
unsigned long __gu_val; \
|
||||
__chk_user_ptr(ptr); \
|
||||
might_fault(); \
|
||||
switch (sizeof(*(ptr))) { \
|
||||
case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \
|
||||
case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \
|
||||
@ -300,6 +327,7 @@ do { \
|
||||
unsigned long __pu_addr = (unsigned long)(ptr); \
|
||||
__typeof__(*(ptr)) __pu_val = (x); \
|
||||
__chk_user_ptr(ptr); \
|
||||
might_fault(); \
|
||||
switch (sizeof(*(ptr))) { \
|
||||
case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \
|
||||
case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \
|
||||
|
@ -159,6 +159,12 @@ static int debug_arch_supported(void)
|
||||
arch >= ARM_DEBUG_ARCH_V7_1;
|
||||
}
|
||||
|
||||
/* Can we determine the watchpoint access type from the fsr? */
|
||||
static int debug_exception_updates_fsr(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Determine number of WRP registers available. */
|
||||
static int get_num_wrp_resources(void)
|
||||
{
|
||||
@ -604,13 +610,14 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
|
||||
/* Aligned */
|
||||
break;
|
||||
case 1:
|
||||
/* Allow single byte watchpoint. */
|
||||
if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
|
||||
break;
|
||||
case 2:
|
||||
/* Allow halfword watchpoints and breakpoints. */
|
||||
if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
|
||||
break;
|
||||
case 3:
|
||||
/* Allow single byte watchpoint. */
|
||||
if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
@ -619,18 +626,35 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
|
||||
info->address &= ~alignment_mask;
|
||||
info->ctrl.len <<= offset;
|
||||
|
||||
/*
|
||||
* Currently we rely on an overflow handler to take
|
||||
* care of single-stepping the breakpoint when it fires.
|
||||
* In the case of userspace breakpoints on a core with V7 debug,
|
||||
* we can use the mismatch feature as a poor-man's hardware
|
||||
* single-step, but this only works for per-task breakpoints.
|
||||
*/
|
||||
if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) ||
|
||||
!core_has_mismatch_brps() || !bp->hw.bp_target)) {
|
||||
pr_warning("overflow handler required but none found\n");
|
||||
ret = -EINVAL;
|
||||
if (!bp->overflow_handler) {
|
||||
/*
|
||||
* Mismatch breakpoints are required for single-stepping
|
||||
* breakpoints.
|
||||
*/
|
||||
if (!core_has_mismatch_brps())
|
||||
return -EINVAL;
|
||||
|
||||
/* We don't allow mismatch breakpoints in kernel space. */
|
||||
if (arch_check_bp_in_kernelspace(bp))
|
||||
return -EPERM;
|
||||
|
||||
/*
|
||||
* Per-cpu breakpoints are not supported by our stepping
|
||||
* mechanism.
|
||||
*/
|
||||
if (!bp->hw.bp_target)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* We only support specific access types if the fsr
|
||||
* reports them.
|
||||
*/
|
||||
if (!debug_exception_updates_fsr() &&
|
||||
(info->ctrl.type == ARM_BREAKPOINT_LOAD ||
|
||||
info->ctrl.type == ARM_BREAKPOINT_STORE))
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
@ -706,10 +730,12 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,
|
||||
goto unlock;
|
||||
|
||||
/* Check that the access type matches. */
|
||||
access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W :
|
||||
HW_BREAKPOINT_R;
|
||||
if (!(access & hw_breakpoint_type(wp)))
|
||||
goto unlock;
|
||||
if (debug_exception_updates_fsr()) {
|
||||
access = (fsr & ARM_FSR_ACCESS_MASK) ?
|
||||
HW_BREAKPOINT_W : HW_BREAKPOINT_R;
|
||||
if (!(access & hw_breakpoint_type(wp)))
|
||||
goto unlock;
|
||||
}
|
||||
|
||||
/* We have a winner. */
|
||||
info->trigger = addr;
|
||||
|
@ -420,20 +420,23 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
|
||||
#endif
|
||||
instr = *(u32 *) pc;
|
||||
} else if (thumb_mode(regs)) {
|
||||
get_user(instr, (u16 __user *)pc);
|
||||
if (get_user(instr, (u16 __user *)pc))
|
||||
goto die_sig;
|
||||
if (is_wide_instruction(instr)) {
|
||||
unsigned int instr2;
|
||||
get_user(instr2, (u16 __user *)pc+1);
|
||||
if (get_user(instr2, (u16 __user *)pc+1))
|
||||
goto die_sig;
|
||||
instr <<= 16;
|
||||
instr |= instr2;
|
||||
}
|
||||
} else {
|
||||
get_user(instr, (u32 __user *)pc);
|
||||
} else if (get_user(instr, (u32 __user *)pc)) {
|
||||
goto die_sig;
|
||||
}
|
||||
|
||||
if (call_undef_hook(regs, instr) == 0)
|
||||
return;
|
||||
|
||||
die_sig:
|
||||
#ifdef CONFIG_DEBUG_USER
|
||||
if (user_debug & UDBG_UNDEFINED) {
|
||||
printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n",
|
||||
|
@ -59,6 +59,7 @@ void __init init_current_timer_delay(unsigned long freq)
|
||||
{
|
||||
pr_info("Switching to timer-based delay loop\n");
|
||||
lpj_fine = freq / HZ;
|
||||
loops_per_jiffy = lpj_fine;
|
||||
arm_delay_ops.delay = __timer_delay;
|
||||
arm_delay_ops.const_udelay = __timer_const_udelay;
|
||||
arm_delay_ops.udelay = __timer_udelay;
|
||||
|
@ -16,8 +16,9 @@
|
||||
* __get_user_X
|
||||
*
|
||||
* Inputs: r0 contains the address
|
||||
* r1 contains the address limit, which must be preserved
|
||||
* Outputs: r0 is the error code
|
||||
* r2, r3 contains the zero-extended value
|
||||
* r2 contains the zero-extended value
|
||||
* lr corrupted
|
||||
*
|
||||
* No other registers must be altered. (see <asm/uaccess.h>
|
||||
@ -27,33 +28,39 @@
|
||||
* Note also that it is intended that __get_user_bad is not global.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/domain.h>
|
||||
|
||||
ENTRY(__get_user_1)
|
||||
check_uaccess r0, 1, r1, r2, __get_user_bad
|
||||
1: TUSER(ldrb) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__get_user_1)
|
||||
|
||||
ENTRY(__get_user_2)
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
2: TUSER(ldrb) r2, [r0]
|
||||
3: TUSER(ldrb) r3, [r0, #1]
|
||||
check_uaccess r0, 2, r1, r2, __get_user_bad
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
rb .req ip
|
||||
2: ldrbt r2, [r0], #1
|
||||
3: ldrbt rb, [r0], #0
|
||||
#else
|
||||
2: TUSER(ldrb) r2, [r0], #1
|
||||
3: TUSER(ldrb) r3, [r0]
|
||||
rb .req r0
|
||||
2: ldrb r2, [r0]
|
||||
3: ldrb rb, [r0, #1]
|
||||
#endif
|
||||
#ifndef __ARMEB__
|
||||
orr r2, r2, r3, lsl #8
|
||||
orr r2, r2, rb, lsl #8
|
||||
#else
|
||||
orr r2, r3, r2, lsl #8
|
||||
orr r2, rb, r2, lsl #8
|
||||
#endif
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__get_user_2)
|
||||
|
||||
ENTRY(__get_user_4)
|
||||
check_uaccess r0, 4, r1, r2, __get_user_bad
|
||||
4: TUSER(ldr) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
|
@ -16,6 +16,7 @@
|
||||
* __put_user_X
|
||||
*
|
||||
* Inputs: r0 contains the address
|
||||
* r1 contains the address limit, which must be preserved
|
||||
* r2, r3 contains the value
|
||||
* Outputs: r0 is the error code
|
||||
* lr corrupted
|
||||
@ -27,16 +28,19 @@
|
||||
* Note also that it is intended that __put_user_bad is not global.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/domain.h>
|
||||
|
||||
ENTRY(__put_user_1)
|
||||
check_uaccess r0, 1, r1, ip, __put_user_bad
|
||||
1: TUSER(strb) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__put_user_1)
|
||||
|
||||
ENTRY(__put_user_2)
|
||||
check_uaccess r0, 2, r1, ip, __put_user_bad
|
||||
mov ip, r2, lsr #8
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
#ifndef __ARMEB__
|
||||
@ -60,12 +64,14 @@ ENTRY(__put_user_2)
|
||||
ENDPROC(__put_user_2)
|
||||
|
||||
ENTRY(__put_user_4)
|
||||
check_uaccess r0, 4, r1, ip, __put_user_bad
|
||||
4: TUSER(str) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__put_user_4)
|
||||
|
||||
ENTRY(__put_user_8)
|
||||
check_uaccess r0, 8, r1, ip, __put_user_bad
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
5: TUSER(str) r2, [r0]
|
||||
6: TUSER(str) r3, [r0, #4]
|
||||
|
@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void)
|
||||
at91_st_read(AT91_ST_SR);
|
||||
|
||||
/* Make IRQs happen for the system timer */
|
||||
setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
|
||||
setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
|
||||
|
||||
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
|
||||
* directly for the clocksource and all clockevents, after adjusting
|
||||
|
@ -726,6 +726,8 @@ static struct resource rtt_resources[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
@ -744,10 +746,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
||||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9260_rtt_device.num_resources = 2;
|
||||
at91sam9260_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
@ -609,6 +609,8 @@ static struct resource rtt_resources[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
@ -626,10 +628,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
||||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9261_rtt_device.num_resources = 2;
|
||||
at91sam9261_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
@ -990,6 +990,8 @@ static struct resource rtt0_resources[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
@ -1006,6 +1008,8 @@ static struct resource rtt1_resources[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
@ -1027,14 +1031,14 @@ static void __init at91_add_device_rtt_rtc(void)
|
||||
* The second resource is needed only for the chosen RTT:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9263_rtt0_device.num_resources = 2;
|
||||
at91sam9263_rtt0_device.num_resources = 3;
|
||||
at91sam9263_rtt1_device.num_resources = 1;
|
||||
pdev = &at91sam9263_rtt0_device;
|
||||
r = rtt0_resources;
|
||||
break;
|
||||
case 1:
|
||||
at91sam9263_rtt0_device.num_resources = 1;
|
||||
at91sam9263_rtt1_device.num_resources = 2;
|
||||
at91sam9263_rtt1_device.num_resources = 3;
|
||||
pdev = &at91sam9263_rtt1_device;
|
||||
r = rtt1_resources;
|
||||
break;
|
||||
@ -1047,6 +1051,8 @@ static void __init at91_add_device_rtt_rtc(void)
|
||||
pdev->name = "rtc-at91sam9";
|
||||
r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
r[1].end = r[1].start + 3;
|
||||
r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
@ -1293,6 +1293,8 @@ static struct resource rtt_resources[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
@ -1310,10 +1312,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
||||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9g45_rtt_device.num_resources = 2;
|
||||
at91sam9g45_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
@ -688,6 +688,8 @@ static struct resource rtt_resources[] = {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
@ -705,10 +707,12 @@ static void __init at91_add_device_rtt_rtc(void)
|
||||
* The second resource is needed:
|
||||
* GPBR will serve as the storage for RTC time offset
|
||||
*/
|
||||
at91sam9rl_rtt_device.num_resources = 2;
|
||||
at91sam9rl_rtt_device.num_resources = 3;
|
||||
rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
|
||||
4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
|
||||
rtt_resources[1].end = rtt_resources[1].start + 3;
|
||||
rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
|
||||
}
|
||||
#else
|
||||
static void __init at91_add_device_rtt_rtc(void)
|
||||
|
@ -63,6 +63,12 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
|
||||
|
||||
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
|
||||
|
||||
#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
|
||||
|| cpu_is_at91sam9263() \
|
||||
|| cpu_is_at91sam9rl())
|
||||
|
||||
#define cpu_has_210M_plla() (cpu_is_at91sam9260())
|
||||
|
||||
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|
||||
|| cpu_is_at91sam9g45() \
|
||||
|| cpu_is_at91sam9x5() \
|
||||
@ -706,6 +712,12 @@ static int __init at91_pmc_init(unsigned long main_clock)
|
||||
} else if (cpu_has_800M_plla()) {
|
||||
if (plla.rate_hz > 800000000)
|
||||
pll_overclock = true;
|
||||
} else if (cpu_has_240M_plla()) {
|
||||
if (plla.rate_hz > 240000000)
|
||||
pll_overclock = true;
|
||||
} else if (cpu_has_210M_plla()) {
|
||||
if (plla.rate_hz > 210000000)
|
||||
pll_overclock = true;
|
||||
} else {
|
||||
if (plla.rate_hz > 209000000)
|
||||
pll_overclock = true;
|
||||
|
@ -102,7 +102,8 @@ void __init dove_ehci1_init(void)
|
||||
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
|
||||
{
|
||||
orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
|
||||
IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR);
|
||||
IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
|
||||
1600);
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
|
@ -42,6 +42,7 @@
|
||||
#include <plat/backlight.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/mfc.h>
|
||||
#include <plat/hdmi.h>
|
||||
|
||||
#include <mach/ohci.h>
|
||||
#include <mach/map.h>
|
||||
@ -734,6 +735,11 @@ static void __init origen_bt_setup(void)
|
||||
s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
/* I2C module and id for HDMIPHY */
|
||||
static struct i2c_board_info hdmiphy_info = {
|
||||
I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
|
||||
};
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
{
|
||||
/* Direct HPD to HDMI chip */
|
||||
@ -781,6 +787,7 @@ static void __init origen_machine_init(void)
|
||||
|
||||
s5p_tv_setup();
|
||||
s5p_i2c_hdmiphy_set_platdata(NULL);
|
||||
s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
|
||||
|
||||
#ifdef CONFIG_DRM_EXYNOS
|
||||
s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
|
||||
|
@ -40,6 +40,7 @@
|
||||
#include <plat/mfc.h>
|
||||
#include <plat/ehci.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/hdmi.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/ohci.h>
|
||||
@ -354,6 +355,11 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
|
||||
.pwm_period_ns = 1000,
|
||||
};
|
||||
|
||||
/* I2C module and id for HDMIPHY */
|
||||
static struct i2c_board_info hdmiphy_info = {
|
||||
I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
|
||||
};
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
{
|
||||
/* direct HPD to HDMI chip */
|
||||
@ -388,6 +394,7 @@ static void __init smdkv310_machine_init(void)
|
||||
|
||||
s5p_tv_setup();
|
||||
s5p_i2c_hdmiphy_set_platdata(NULL);
|
||||
s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
|
||||
|
||||
samsung_keypad_set_platdata(&smdkv310_keypad_data);
|
||||
|
||||
|
@ -17,6 +17,7 @@
|
||||
#include <linux/sched.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/system_misc.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#define IRQ_SOURCE(base_addr) (base_addr + 0x00)
|
||||
|
@ -9,7 +9,8 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
|
||||
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
|
||||
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
|
||||
imx5-pm-$(CONFIG_PM) += pm-imx5.o
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
|
||||
clk-pfd.o clk-busy.o
|
||||
@ -70,14 +71,13 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
|
||||
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
|
||||
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
|
||||
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
|
||||
obj-$(CONFIG_CPU_V7) += head-v7.o
|
||||
AFLAGS_head-v7.o :=-Wa,-march=armv7-a
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
|
||||
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
|
||||
|
||||
ifeq ($(CONFIG_PM),y)
|
||||
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
|
||||
endif
|
||||
|
||||
# i.MX5 based machines
|
||||
|
@ -222,10 +222,8 @@ int __init mx25_clocks_init(void)
|
||||
clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
|
||||
clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
|
||||
clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
|
||||
clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
|
||||
clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
|
||||
|
@ -230,10 +230,8 @@ int __init mx35_clocks_init()
|
||||
clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
|
||||
clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
|
||||
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
|
||||
clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
|
||||
clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
|
||||
/* i.mx35 has the i.mx21 type uart */
|
||||
clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
|
||||
|
@ -152,7 +152,7 @@ enum mx6q_clks {
|
||||
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
|
||||
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
|
||||
pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
|
||||
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2,
|
||||
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
|
||||
clk_max
|
||||
};
|
||||
|
||||
@ -288,8 +288,10 @@ int __init mx6q_clocks_init(void)
|
||||
clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
|
||||
clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
|
||||
clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
|
||||
clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_sel", base + 0x20, 10, 1);
|
||||
clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_sel", base + 0x20, 11, 1);
|
||||
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1);
|
||||
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1);
|
||||
clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
|
||||
clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
|
||||
clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
|
||||
|
@ -42,22 +42,6 @@ static inline void cpu_enter_lowpower(void)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
static inline void cpu_leave_lowpower(void)
|
||||
{
|
||||
unsigned int v;
|
||||
|
||||
asm volatile(
|
||||
"mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" orr %0, %0, %1\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" orr %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
: "=&r" (v)
|
||||
: "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
* platform-specific code to shutdown a CPU
|
||||
*
|
||||
@ -67,11 +51,10 @@ void platform_cpu_die(unsigned int cpu)
|
||||
{
|
||||
cpu_enter_lowpower();
|
||||
imx_enable_cpu(cpu, false);
|
||||
cpu_do_idle();
|
||||
cpu_leave_lowpower();
|
||||
|
||||
/* We should never return from idle */
|
||||
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
|
||||
/* spin here until hardware takes it down */
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
int platform_cpu_disable(unsigned int cpu)
|
||||
|
@ -71,7 +71,7 @@ soft:
|
||||
/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
|
||||
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_PHYLIB)) {
|
||||
if (IS_BUILTIN(CONFIG_PHYLIB)) {
|
||||
/* min rx data delay */
|
||||
phy_write(phydev, 0x0b, 0x8105);
|
||||
phy_write(phydev, 0x0c, 0x0000);
|
||||
@ -112,7 +112,7 @@ put_clk:
|
||||
|
||||
static void __init imx6q_sabrelite_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_PHYLIB))
|
||||
if (IS_BUILTIN(CONFIG_PHYLIB))
|
||||
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
|
||||
ksz9021rn_phy_fixup);
|
||||
imx6q_sabrelite_cko1_setup();
|
||||
|
@ -7,7 +7,8 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
|
||||
dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
|
||||
dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
|
||||
dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
|
||||
dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb
|
||||
dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6281.dtb
|
||||
dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6282.dtb
|
||||
dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
|
||||
dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
|
||||
dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
|
||||
|
@ -301,7 +301,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
|
||||
{
|
||||
orion_ge00_init(eth_data,
|
||||
GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
|
||||
IRQ_KIRKWOOD_GE00_ERR);
|
||||
IRQ_KIRKWOOD_GE00_ERR, 1600);
|
||||
/* The interface forgets the MAC address assigned by u-boot if
|
||||
the clock is turned off, so claim the clk now. */
|
||||
clk_prepare_enable(ge0);
|
||||
@ -315,7 +315,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
|
||||
{
|
||||
orion_ge01_init(eth_data,
|
||||
GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
|
||||
IRQ_KIRKWOOD_GE01_ERR);
|
||||
IRQ_KIRKWOOD_GE01_ERR, 1600);
|
||||
clk_prepare_enable(ge1);
|
||||
}
|
||||
|
||||
@ -517,6 +517,13 @@ void __init kirkwood_wdt_init(void)
|
||||
void __init kirkwood_init_early(void)
|
||||
{
|
||||
orion_time_set_base(TIMER_VIRT_BASE);
|
||||
|
||||
/*
|
||||
* Some Kirkwood devices allocate their coherent buffers from atomic
|
||||
* context. Increase size of atomic coherent pool to make sure such
|
||||
* the allocations won't fail.
|
||||
*/
|
||||
init_dma_coherent_pool_size(SZ_1M);
|
||||
}
|
||||
|
||||
int kirkwood_tclk;
|
||||
|
@ -10,6 +10,7 @@
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/ata_platform.h>
|
||||
|
@ -68,7 +68,7 @@ static int __devinit sram_probe(struct platform_device *pdev)
|
||||
struct resource *res;
|
||||
int ret = 0;
|
||||
|
||||
if (!pdata && !pdata->pool_name)
|
||||
if (!pdata || !pdata->pool_name)
|
||||
return -ENODEV;
|
||||
|
||||
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
||||
|
@ -37,7 +37,7 @@
|
||||
#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
|
||||
#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
|
||||
|
||||
static void __init __iomem *win_cfg_base(int win)
|
||||
static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
|
||||
{
|
||||
/*
|
||||
* Find the control register base address for this window.
|
||||
|
@ -213,7 +213,8 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
|
||||
{
|
||||
orion_ge00_init(eth_data,
|
||||
GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
|
||||
IRQ_MV78XX0_GE_ERR);
|
||||
IRQ_MV78XX0_GE_ERR,
|
||||
MV643XX_TX_CSUM_DEFAULT_LIMIT);
|
||||
}
|
||||
|
||||
|
||||
@ -224,7 +225,8 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
|
||||
{
|
||||
orion_ge01_init(eth_data,
|
||||
GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
|
||||
NO_IRQ);
|
||||
NO_IRQ,
|
||||
MV643XX_TX_CSUM_DEFAULT_LIMIT);
|
||||
}
|
||||
|
||||
|
||||
|
@ -62,13 +62,14 @@ config ARCH_OMAP4
|
||||
select PM_OPP if PM
|
||||
select USB_ARCH_HAS_EHCI if USB_SUPPORT
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
select ARCH_NEEDS_CPU_IDLE_COUPLED
|
||||
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
|
||||
|
||||
config SOC_OMAP5
|
||||
bool "TI OMAP5"
|
||||
select CPU_V7
|
||||
select ARM_GIC
|
||||
select HAVE_SMP
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
|
||||
comment "OMAP Core Type"
|
||||
depends on ARCH_OMAP2
|
||||
@ -231,10 +232,11 @@ config MACH_OMAP3_PANDORA
|
||||
select OMAP_PACKAGE_CBB
|
||||
select REGULATOR_FIXED_VOLTAGE if REGULATOR
|
||||
|
||||
config MACH_OMAP3_TOUCHBOOK
|
||||
config MACH_TOUCHBOOK
|
||||
bool "OMAP3 Touch Book"
|
||||
depends on ARCH_OMAP3
|
||||
default y
|
||||
select OMAP_PACKAGE_CBB
|
||||
|
||||
config MACH_OMAP_3430SDP
|
||||
bool "OMAP 3430 SDP board"
|
||||
|
@ -255,7 +255,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o
|
||||
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
|
||||
obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
|
||||
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
|
||||
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o
|
||||
obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o
|
||||
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
|
||||
obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o
|
||||
|
||||
|
@ -554,6 +554,8 @@ static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
/* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
|
||||
OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
};
|
||||
#endif
|
||||
|
@ -58,6 +58,7 @@
|
||||
#include "hsmmc.h"
|
||||
#include "common-board-devices.h"
|
||||
|
||||
#define OMAP3_EVM_TS_GPIO 175
|
||||
#define OMAP3_EVM_EHCI_VBUS 22
|
||||
#define OMAP3_EVM_EHCI_SELECT 61
|
||||
|
||||
|
@ -1036,13 +1036,13 @@ static struct omap_clk am33xx_clks[] = {
|
||||
CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
|
||||
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
|
||||
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
|
||||
CLK(NULL, "gpt1_fck", &timer1_fck, CK_AM33XX),
|
||||
CLK(NULL, "gpt2_fck", &timer2_fck, CK_AM33XX),
|
||||
CLK(NULL, "gpt3_fck", &timer3_fck, CK_AM33XX),
|
||||
CLK(NULL, "gpt4_fck", &timer4_fck, CK_AM33XX),
|
||||
CLK(NULL, "gpt5_fck", &timer5_fck, CK_AM33XX),
|
||||
CLK(NULL, "gpt6_fck", &timer6_fck, CK_AM33XX),
|
||||
CLK(NULL, "gpt7_fck", &timer7_fck, CK_AM33XX),
|
||||
CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
|
||||
CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
|
||||
CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
|
||||
CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
|
||||
CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
|
||||
CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
|
||||
CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
|
||||
CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
|
||||
CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
|
||||
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
|
||||
|
@ -241,6 +241,52 @@ static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
|
||||
_clkdm_del_autodeps(clkdm);
|
||||
}
|
||||
|
||||
static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
|
||||
{
|
||||
bool hwsup = false;
|
||||
|
||||
if (!clkdm->clktrctrl_mask)
|
||||
return 0;
|
||||
|
||||
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||
clkdm->clktrctrl_mask);
|
||||
|
||||
if (hwsup) {
|
||||
/* Disable HW transitions when we are changing deps */
|
||||
_disable_hwsup(clkdm);
|
||||
_clkdm_add_autodeps(clkdm);
|
||||
_enable_hwsup(clkdm);
|
||||
} else {
|
||||
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
|
||||
omap3_clkdm_wakeup(clkdm);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
|
||||
{
|
||||
bool hwsup = false;
|
||||
|
||||
if (!clkdm->clktrctrl_mask)
|
||||
return 0;
|
||||
|
||||
hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
|
||||
clkdm->clktrctrl_mask);
|
||||
|
||||
if (hwsup) {
|
||||
/* Disable HW transitions when we are changing deps */
|
||||
_disable_hwsup(clkdm);
|
||||
_clkdm_del_autodeps(clkdm);
|
||||
_enable_hwsup(clkdm);
|
||||
} else {
|
||||
if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
|
||||
omap3_clkdm_sleep(clkdm);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct clkdm_ops omap2_clkdm_operations = {
|
||||
.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
|
||||
.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
|
||||
@ -267,6 +313,6 @@ struct clkdm_ops omap3_clkdm_operations = {
|
||||
.clkdm_wakeup = omap3_clkdm_wakeup,
|
||||
.clkdm_allow_idle = omap3_clkdm_allow_idle,
|
||||
.clkdm_deny_idle = omap3_clkdm_deny_idle,
|
||||
.clkdm_clk_enable = omap2_clkdm_clk_enable,
|
||||
.clkdm_clk_disable = omap2_clkdm_clk_disable,
|
||||
.clkdm_clk_enable = omap3xxx_clkdm_clk_enable,
|
||||
.clkdm_clk_disable = omap3xxx_clkdm_clk_disable,
|
||||
};
|
||||
|
@ -67,6 +67,7 @@
|
||||
#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
|
||||
|
||||
/* CM_IDLEST_IVA2 */
|
||||
#define OMAP3430_ST_IVA2_SHIFT 0
|
||||
#define OMAP3430_ST_IVA2_MASK (1 << 0)
|
||||
|
||||
/* CM_IDLEST_PLL_IVA2 */
|
||||
|
@ -35,16 +35,6 @@ static struct omap2_mcspi_device_config ads7846_mcspi_config = {
|
||||
.turbo_mode = 0,
|
||||
};
|
||||
|
||||
/*
|
||||
* ADS7846 driver maybe request a gpio according to the value
|
||||
* of pdata->get_pendown_state, but we have done this. So set
|
||||
* get_pendown_state to avoid twice gpio requesting.
|
||||
*/
|
||||
static int omap3_get_pendown_state(void)
|
||||
{
|
||||
return !gpio_get_value(OMAP3_EVM_TS_GPIO);
|
||||
}
|
||||
|
||||
static struct ads7846_platform_data ads7846_config = {
|
||||
.x_max = 0x0fff,
|
||||
.y_max = 0x0fff,
|
||||
@ -55,7 +45,6 @@ static struct ads7846_platform_data ads7846_config = {
|
||||
.debounce_rep = 1,
|
||||
.gpio_pendown = -EINVAL,
|
||||
.keep_vref_on = 1,
|
||||
.get_pendown_state = &omap3_get_pendown_state,
|
||||
};
|
||||
|
||||
static struct spi_board_info ads7846_spi_board_info __initdata = {
|
||||
|
@ -4,7 +4,6 @@
|
||||
#include "twl-common.h"
|
||||
|
||||
#define NAND_BLOCK_SIZE SZ_128K
|
||||
#define OMAP3_EVM_TS_GPIO 175
|
||||
|
||||
struct mtd_partition;
|
||||
struct ads7846_platform_data;
|
||||
|
@ -238,8 +238,9 @@ int __init omap4_idle_init(void)
|
||||
for_each_cpu(cpu_id, cpu_online_mask) {
|
||||
dev = &per_cpu(omap4_idle_dev, cpu_id);
|
||||
dev->cpu = cpu_id;
|
||||
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
|
||||
dev->coupled_cpus = *cpu_online_mask;
|
||||
|
||||
#endif
|
||||
cpuidle_register_driver(&omap4_idle_driver);
|
||||
|
||||
if (cpuidle_register_device(dev)) {
|
||||
|
@ -127,7 +127,6 @@ struct omap_mux_partition {
|
||||
* @gpio: GPIO number
|
||||
* @muxnames: available signal modes for a ball
|
||||
* @balls: available balls on the package
|
||||
* @partition: mux partition
|
||||
*/
|
||||
struct omap_mux {
|
||||
u16 reg_offset;
|
||||
|
@ -46,7 +46,7 @@
|
||||
static void __iomem *wakeupgen_base;
|
||||
static void __iomem *sar_base;
|
||||
static DEFINE_SPINLOCK(wakeupgen_lock);
|
||||
static unsigned int irq_target_cpu[NR_IRQS];
|
||||
static unsigned int irq_target_cpu[MAX_IRQS];
|
||||
static unsigned int irq_banks = MAX_NR_REG_BANKS;
|
||||
static unsigned int max_irqs = MAX_IRQS;
|
||||
static unsigned int omap_secure_apis;
|
||||
|
@ -1889,6 +1889,7 @@ static int _enable(struct omap_hwmod *oh)
|
||||
_enable_sysc(oh);
|
||||
}
|
||||
} else {
|
||||
_omap4_disable_module(oh);
|
||||
_disable_clocks(oh);
|
||||
pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
|
||||
oh->name, r);
|
||||
|
@ -100,9 +100,9 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
|
||||
|
||||
/* IVA2 (IVA2) */
|
||||
static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
|
||||
{ .name = "logic", .rst_shift = 0 },
|
||||
{ .name = "seq0", .rst_shift = 1 },
|
||||
{ .name = "seq1", .rst_shift = 2 },
|
||||
{ .name = "logic", .rst_shift = 0, .st_shift = 8 },
|
||||
{ .name = "seq0", .rst_shift = 1, .st_shift = 9 },
|
||||
{ .name = "seq1", .rst_shift = 2, .st_shift = 10 },
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap3xxx_iva_hwmod = {
|
||||
@ -112,6 +112,15 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
|
||||
.rst_lines = omap3xxx_iva_resets,
|
||||
.rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
|
||||
.main_clk = "iva2_ck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = OMAP3430_IVA2_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
/* timer class */
|
||||
|
@ -4210,7 +4210,7 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
|
||||
};
|
||||
|
||||
/* dsp -> sl2if */
|
||||
static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
|
||||
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
|
||||
.master = &omap44xx_dsp_hwmod,
|
||||
.slave = &omap44xx_sl2if_hwmod,
|
||||
.clk = "dpll_iva_m5x2_ck",
|
||||
@ -4828,7 +4828,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
|
||||
};
|
||||
|
||||
/* iva -> sl2if */
|
||||
static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
|
||||
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
|
||||
.master = &omap44xx_iva_hwmod,
|
||||
.slave = &omap44xx_sl2if_hwmod,
|
||||
.clk = "dpll_iva_m5x2_ck",
|
||||
@ -5362,7 +5362,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
|
||||
};
|
||||
|
||||
/* l3_main_2 -> sl2if */
|
||||
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
|
||||
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
|
||||
.master = &omap44xx_l3_main_2_hwmod,
|
||||
.slave = &omap44xx_sl2if_hwmod,
|
||||
.clk = "l3_div_ck",
|
||||
@ -6032,7 +6032,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_l4_abe__dmic,
|
||||
&omap44xx_l4_abe__dmic_dma,
|
||||
&omap44xx_dsp__iva,
|
||||
&omap44xx_dsp__sl2if,
|
||||
/* &omap44xx_dsp__sl2if, */
|
||||
&omap44xx_l4_cfg__dsp,
|
||||
&omap44xx_l3_main_2__dss,
|
||||
&omap44xx_l4_per__dss,
|
||||
@ -6068,7 +6068,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_l4_per__i2c4,
|
||||
&omap44xx_l3_main_2__ipu,
|
||||
&omap44xx_l3_main_2__iss,
|
||||
&omap44xx_iva__sl2if,
|
||||
/* &omap44xx_iva__sl2if, */
|
||||
&omap44xx_l3_main_2__iva,
|
||||
&omap44xx_l4_wkup__kbd,
|
||||
&omap44xx_l4_cfg__mailbox,
|
||||
@ -6099,7 +6099,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
|
||||
&omap44xx_l4_cfg__cm_core,
|
||||
&omap44xx_l4_wkup__prm,
|
||||
&omap44xx_l4_wkup__scrm,
|
||||
&omap44xx_l3_main_2__sl2if,
|
||||
/* &omap44xx_l3_main_2__sl2if, */
|
||||
&omap44xx_l4_abe__slimbus1,
|
||||
&omap44xx_l4_abe__slimbus1_dma,
|
||||
&omap44xx_l4_per__slimbus2,
|
||||
|
@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
|
||||
{
|
||||
int r = -ENODEV;
|
||||
|
||||
if (!cpu_is_omap44xx())
|
||||
if (!cpu_is_omap443x())
|
||||
return r;
|
||||
|
||||
r = omap_init_opp_table(omap44xx_opp_def_list,
|
||||
|
@ -272,21 +272,16 @@ void omap_sram_idle(void)
|
||||
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
|
||||
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
|
||||
|
||||
if (mpu_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_pre_transition(mpu_pwrdm);
|
||||
pwrdm_pre_transition(neon_pwrdm);
|
||||
}
|
||||
pwrdm_pre_transition(NULL);
|
||||
|
||||
/* PER */
|
||||
if (per_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_pre_transition(per_pwrdm);
|
||||
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
|
||||
omap2_gpio_prepare_for_idle(per_going_off);
|
||||
}
|
||||
|
||||
/* CORE */
|
||||
if (core_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_pre_transition(core_pwrdm);
|
||||
if (core_next_state == PWRDM_POWER_OFF) {
|
||||
omap3_core_save_context();
|
||||
omap3_cm_save_context();
|
||||
@ -339,20 +334,14 @@ void omap_sram_idle(void)
|
||||
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_VOLTCTRL_OFFSET);
|
||||
pwrdm_post_transition(core_pwrdm);
|
||||
}
|
||||
omap3_intc_resume_idle();
|
||||
|
||||
/* PER */
|
||||
if (per_next_state < PWRDM_POWER_ON) {
|
||||
omap2_gpio_resume_after_idle();
|
||||
pwrdm_post_transition(per_pwrdm);
|
||||
}
|
||||
pwrdm_post_transition(NULL);
|
||||
|
||||
if (mpu_next_state < PWRDM_POWER_ON) {
|
||||
pwrdm_post_transition(mpu_pwrdm);
|
||||
pwrdm_post_transition(neon_pwrdm);
|
||||
}
|
||||
/* PER */
|
||||
if (per_next_state < PWRDM_POWER_ON)
|
||||
omap2_gpio_resume_after_idle();
|
||||
}
|
||||
|
||||
static void omap3_pm_idle(void)
|
||||
|
@ -56,9 +56,13 @@ ppa_por_params:
|
||||
* The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
|
||||
* It returns to the caller for CPU INACTIVE and ON power states or in case
|
||||
* CPU failed to transition to targeted OFF/DORMANT state.
|
||||
*
|
||||
* omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
|
||||
* stack frame and it expects the caller to take care of it. Hence the entire
|
||||
* stack frame is saved to avoid possible stack corruption.
|
||||
*/
|
||||
ENTRY(omap4_finish_suspend)
|
||||
stmfd sp!, {lr}
|
||||
stmfd sp!, {r4-r12, lr}
|
||||
cmp r0, #0x0
|
||||
beq do_WFI @ No lowpower state, jump to WFI
|
||||
|
||||
@ -226,7 +230,7 @@ scu_gp_clear:
|
||||
skip_scu_gp_clear:
|
||||
isb
|
||||
dsb
|
||||
ldmfd sp!, {pc}
|
||||
ldmfd sp!, {r4-r12, pc}
|
||||
ENDPROC(omap4_finish_suspend)
|
||||
|
||||
/*
|
||||
|
@ -260,6 +260,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_32K_TIMER
|
||||
/* Setup free-running counter for clocksource */
|
||||
static int __init omap2_sync32k_clocksource_init(void)
|
||||
{
|
||||
@ -299,6 +300,12 @@ static int __init omap2_sync32k_clocksource_init(void)
|
||||
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
static inline int omap2_sync32k_clocksource_init(void)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void __init omap2_gptimer_clocksource_init(int gptimer_id,
|
||||
const char *fck_source)
|
||||
|
@ -67,6 +67,7 @@ void __init omap_pmic_init(int bus, u32 clkrate,
|
||||
const char *pmic_type, int pmic_irq,
|
||||
struct twl4030_platform_data *pmic_data)
|
||||
{
|
||||
omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
|
||||
strncpy(pmic_i2c_board_info.type, pmic_type,
|
||||
sizeof(pmic_i2c_board_info.type));
|
||||
pmic_i2c_board_info.irq = pmic_irq;
|
||||
|
@ -109,7 +109,8 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
|
||||
{
|
||||
orion_ge00_init(eth_data,
|
||||
ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
|
||||
IRQ_ORION5X_ETH_ERR);
|
||||
IRQ_ORION5X_ETH_ERR,
|
||||
MV643XX_TX_CSUM_DEFAULT_LIMIT);
|
||||
}
|
||||
|
||||
|
||||
|
@ -24,7 +24,8 @@
|
||||
*/
|
||||
|
||||
enum dma_ch {
|
||||
DMACH_XD0,
|
||||
DMACH_DT_PROP = -1, /* not yet supported, do not use */
|
||||
DMACH_XD0 = 0,
|
||||
DMACH_XD1,
|
||||
DMACH_SDI,
|
||||
DMACH_SPI0,
|
||||
|
@ -520,13 +520,14 @@ static struct platform_device hdmi_lcdc_device = {
|
||||
};
|
||||
|
||||
/* GPIO KEY */
|
||||
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
|
||||
#define GPIO_KEY(c, g, d, ...) \
|
||||
{ .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
|
||||
|
||||
static struct gpio_keys_button gpio_buttons[] = {
|
||||
GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW1"),
|
||||
GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW2"),
|
||||
GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW3"),
|
||||
GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW4"),
|
||||
GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1),
|
||||
GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"),
|
||||
GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"),
|
||||
GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"),
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data gpio_key_info = {
|
||||
@ -901,8 +902,8 @@ static struct platform_device *eva_devices[] __initdata = {
|
||||
&camera_device,
|
||||
&ceu0_device,
|
||||
&fsi_device,
|
||||
&fsi_hdmi_device,
|
||||
&fsi_wm8978_device,
|
||||
&fsi_hdmi_device,
|
||||
};
|
||||
|
||||
static void __init eva_clock_init(void)
|
||||
|
@ -695,6 +695,7 @@ static struct platform_device usbhs0_device = {
|
||||
* - J30 "open"
|
||||
* - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
|
||||
* - add .get_vbus = usbhs_get_vbus in usbhs1_private
|
||||
* - check usbhs0_device(pio)/usbhs1_device(irq) order in mackerel_devices.
|
||||
*/
|
||||
#define IRQ8 evt2irq(0x0300)
|
||||
#define USB_PHY_MODE (1 << 4)
|
||||
@ -1325,8 +1326,8 @@ static struct platform_device *mackerel_devices[] __initdata = {
|
||||
&nor_flash_device,
|
||||
&smc911x_device,
|
||||
&lcdc_device,
|
||||
&usbhs1_device,
|
||||
&usbhs0_device,
|
||||
&usbhs1_device,
|
||||
&leds_device,
|
||||
&fsi_device,
|
||||
&fsi_ak4643_device,
|
||||
|
@ -67,7 +67,7 @@ static struct smsc911x_platform_config smsc911x_platdata = {
|
||||
|
||||
static struct platform_device eth_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_platdata,
|
||||
},
|
||||
|
@ -259,9 +259,9 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
|
||||
return 0; /* always allow wakeup */
|
||||
}
|
||||
|
||||
#define RELOC_BASE 0x1000
|
||||
#define RELOC_BASE 0x1200
|
||||
|
||||
/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
|
||||
/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
|
||||
#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
|
@ -41,7 +41,6 @@ config MACH_HREFV60
|
||||
config MACH_SNOWBALL
|
||||
bool "U8500 Snowball platform"
|
||||
select MACH_MOP500
|
||||
select LEDS_GPIO
|
||||
help
|
||||
Include support for the snowball development platform.
|
||||
|
||||
|
@ -191,9 +191,9 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
|
||||
return pdev;
|
||||
}
|
||||
|
||||
/* Platform device for ASoC U8500 machine */
|
||||
static struct platform_device snd_soc_u8500 = {
|
||||
.name = "snd-soc-u8500",
|
||||
/* Platform device for ASoC MOP500 machine */
|
||||
static struct platform_device snd_soc_mop500 = {
|
||||
.name = "snd-soc-mop500",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = NULL,
|
||||
@ -227,8 +227,8 @@ int mop500_msp_init(struct device *parent)
|
||||
{
|
||||
struct platform_device *msp1;
|
||||
|
||||
pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
|
||||
platform_device_register(&snd_soc_u8500);
|
||||
pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
|
||||
platform_device_register(&snd_soc_mop500);
|
||||
|
||||
pr_info("Initialize MSP I2S-devices.\n");
|
||||
db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
|
||||
|
@ -797,6 +797,7 @@ static void __init u8500_init_machine(void)
|
||||
ARRAY_SIZE(mop500_platform_devs));
|
||||
|
||||
mop500_sdi_init(parent);
|
||||
mop500_msp_init(parent);
|
||||
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
|
||||
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
|
||||
i2c_register_board_info(2, mop500_i2c2_devices,
|
||||
@ -804,6 +805,8 @@ static void __init u8500_init_machine(void)
|
||||
|
||||
mop500_uib_init();
|
||||
|
||||
} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
|
||||
mop500_msp_init(parent);
|
||||
} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
|
||||
/*
|
||||
* The HREFv60 board removed a GPIO expander and routed
|
||||
@ -815,6 +818,7 @@ static void __init u8500_init_machine(void)
|
||||
ARRAY_SIZE(mop500_platform_devs));
|
||||
|
||||
hrefv60_sdi_init(parent);
|
||||
mop500_msp_init(parent);
|
||||
|
||||
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
|
||||
i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
|
||||
|
@ -63,10 +63,11 @@ static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd,
|
||||
pid = task_pid_nr(thread->task) << ASID_BITS;
|
||||
asm volatile(
|
||||
" mrc p15, 0, %0, c13, c0, 1\n"
|
||||
" bfi %1, %0, #0, %2\n"
|
||||
" mcr p15, 0, %1, c13, c0, 1\n"
|
||||
" and %0, %0, %2\n"
|
||||
" orr %0, %0, %1\n"
|
||||
" mcr p15, 0, %0, c13, c0, 1\n"
|
||||
: "=r" (contextidr), "+r" (pid)
|
||||
: "I" (ASID_BITS));
|
||||
: "I" (~ASID_MASK));
|
||||
isb();
|
||||
|
||||
return NOTIFY_OK;
|
||||
|
@ -267,17 +267,19 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
|
||||
vunmap(cpu_addr);
|
||||
}
|
||||
|
||||
#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
|
||||
|
||||
struct dma_pool {
|
||||
size_t size;
|
||||
spinlock_t lock;
|
||||
unsigned long *bitmap;
|
||||
unsigned long nr_pages;
|
||||
void *vaddr;
|
||||
struct page *page;
|
||||
struct page **pages;
|
||||
};
|
||||
|
||||
static struct dma_pool atomic_pool = {
|
||||
.size = SZ_256K,
|
||||
.size = DEFAULT_DMA_COHERENT_POOL_SIZE,
|
||||
};
|
||||
|
||||
static int __init early_coherent_pool(char *p)
|
||||
@ -287,6 +289,21 @@ static int __init early_coherent_pool(char *p)
|
||||
}
|
||||
early_param("coherent_pool", early_coherent_pool);
|
||||
|
||||
void __init init_dma_coherent_pool_size(unsigned long size)
|
||||
{
|
||||
/*
|
||||
* Catch any attempt to set the pool size too late.
|
||||
*/
|
||||
BUG_ON(atomic_pool.vaddr);
|
||||
|
||||
/*
|
||||
* Set architecture specific coherent pool size only if
|
||||
* it has not been changed by kernel command line parameter.
|
||||
*/
|
||||
if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
|
||||
atomic_pool.size = size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise the coherent pool for atomic allocations.
|
||||
*/
|
||||
@ -297,6 +314,7 @@ static int __init atomic_pool_init(void)
|
||||
unsigned long nr_pages = pool->size >> PAGE_SHIFT;
|
||||
unsigned long *bitmap;
|
||||
struct page *page;
|
||||
struct page **pages;
|
||||
void *ptr;
|
||||
int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
|
||||
|
||||
@ -304,21 +322,31 @@ static int __init atomic_pool_init(void)
|
||||
if (!bitmap)
|
||||
goto no_bitmap;
|
||||
|
||||
pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
|
||||
if (!pages)
|
||||
goto no_pages;
|
||||
|
||||
if (IS_ENABLED(CONFIG_CMA))
|
||||
ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
|
||||
else
|
||||
ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
|
||||
&page, NULL);
|
||||
if (ptr) {
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nr_pages; i++)
|
||||
pages[i] = page + i;
|
||||
|
||||
spin_lock_init(&pool->lock);
|
||||
pool->vaddr = ptr;
|
||||
pool->page = page;
|
||||
pool->pages = pages;
|
||||
pool->bitmap = bitmap;
|
||||
pool->nr_pages = nr_pages;
|
||||
pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
|
||||
(unsigned)pool->size / 1024);
|
||||
return 0;
|
||||
}
|
||||
no_pages:
|
||||
kfree(bitmap);
|
||||
no_bitmap:
|
||||
pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
|
||||
@ -443,27 +471,45 @@ static void *__alloc_from_pool(size_t size, struct page **ret_page)
|
||||
if (pageno < pool->nr_pages) {
|
||||
bitmap_set(pool->bitmap, pageno, count);
|
||||
ptr = pool->vaddr + PAGE_SIZE * pageno;
|
||||
*ret_page = pool->page + pageno;
|
||||
*ret_page = pool->pages[pageno];
|
||||
} else {
|
||||
pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
|
||||
"Please increase it with coherent_pool= kernel parameter!\n",
|
||||
(unsigned)pool->size / 1024);
|
||||
}
|
||||
spin_unlock_irqrestore(&pool->lock, flags);
|
||||
|
||||
return ptr;
|
||||
}
|
||||
|
||||
static bool __in_atomic_pool(void *start, size_t size)
|
||||
{
|
||||
struct dma_pool *pool = &atomic_pool;
|
||||
void *end = start + size;
|
||||
void *pool_start = pool->vaddr;
|
||||
void *pool_end = pool->vaddr + pool->size;
|
||||
|
||||
if (start < pool_start || start >= pool_end)
|
||||
return false;
|
||||
|
||||
if (end <= pool_end)
|
||||
return true;
|
||||
|
||||
WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
|
||||
start, end - 1, pool_start, pool_end - 1);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int __free_from_pool(void *start, size_t size)
|
||||
{
|
||||
struct dma_pool *pool = &atomic_pool;
|
||||
unsigned long pageno, count;
|
||||
unsigned long flags;
|
||||
|
||||
if (start < pool->vaddr || start > pool->vaddr + pool->size)
|
||||
if (!__in_atomic_pool(start, size))
|
||||
return 0;
|
||||
|
||||
if (start + size > pool->vaddr + pool->size) {
|
||||
WARN(1, "freeing wrong coherent size from pool\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
pageno = (start - pool->vaddr) >> PAGE_SHIFT;
|
||||
count = size >> PAGE_SHIFT;
|
||||
|
||||
@ -1090,10 +1136,22 @@ static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t si
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct page **__atomic_get_pages(void *addr)
|
||||
{
|
||||
struct dma_pool *pool = &atomic_pool;
|
||||
struct page **pages = pool->pages;
|
||||
int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
|
||||
|
||||
return pages + offs;
|
||||
}
|
||||
|
||||
static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
|
||||
{
|
||||
struct vm_struct *area;
|
||||
|
||||
if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
|
||||
return __atomic_get_pages(cpu_addr);
|
||||
|
||||
if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
|
||||
return cpu_addr;
|
||||
|
||||
@ -1103,6 +1161,34 @@ static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void *__iommu_alloc_atomic(struct device *dev, size_t size,
|
||||
dma_addr_t *handle)
|
||||
{
|
||||
struct page *page;
|
||||
void *addr;
|
||||
|
||||
addr = __alloc_from_pool(size, &page);
|
||||
if (!addr)
|
||||
return NULL;
|
||||
|
||||
*handle = __iommu_create_mapping(dev, &page, size);
|
||||
if (*handle == DMA_ERROR_CODE)
|
||||
goto err_mapping;
|
||||
|
||||
return addr;
|
||||
|
||||
err_mapping:
|
||||
__free_from_pool(addr, size);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void __iommu_free_atomic(struct device *dev, struct page **pages,
|
||||
dma_addr_t handle, size_t size)
|
||||
{
|
||||
__iommu_remove_mapping(dev, handle, size);
|
||||
__free_from_pool(page_address(pages[0]), size);
|
||||
}
|
||||
|
||||
static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
|
||||
dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
|
||||
{
|
||||
@ -1113,6 +1199,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
|
||||
*handle = DMA_ERROR_CODE;
|
||||
size = PAGE_ALIGN(size);
|
||||
|
||||
if (gfp & GFP_ATOMIC)
|
||||
return __iommu_alloc_atomic(dev, size, handle);
|
||||
|
||||
pages = __iommu_alloc_buffer(dev, size, gfp);
|
||||
if (!pages)
|
||||
return NULL;
|
||||
@ -1179,6 +1268,11 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
|
||||
return;
|
||||
}
|
||||
|
||||
if (__in_atomic_pool(cpu_addr, size)) {
|
||||
__iommu_free_atomic(dev, pages, handle, size);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
|
||||
unmap_kernel_range((unsigned long)cpu_addr, size);
|
||||
vunmap(cpu_addr);
|
||||
|
@ -55,6 +55,9 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
|
||||
/* permanent static mappings from iotable_init() */
|
||||
#define VM_ARM_STATIC_MAPPING 0x40000000
|
||||
|
||||
/* empty mapping */
|
||||
#define VM_ARM_EMPTY_MAPPING 0x20000000
|
||||
|
||||
/* mapping type (attributes) for permanent static mappings */
|
||||
#define VM_ARM_MTYPE(mt) ((mt) << 20)
|
||||
#define VM_ARM_MTYPE_MASK (0x1f << 20)
|
||||
|
@ -807,7 +807,7 @@ static void __init pmd_empty_section_gap(unsigned long addr)
|
||||
vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
|
||||
vm->addr = (void *)addr;
|
||||
vm->size = SECTION_SIZE;
|
||||
vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
|
||||
vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
|
||||
vm->caller = pmd_empty_section_gap;
|
||||
vm_area_add_early(vm);
|
||||
}
|
||||
@ -820,7 +820,7 @@ static void __init fill_pmd_gaps(void)
|
||||
|
||||
/* we're still single threaded hence no lock needed here */
|
||||
for (vm = vmlist; vm; vm = vm->next) {
|
||||
if (!(vm->flags & VM_ARM_STATIC_MAPPING))
|
||||
if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING)))
|
||||
continue;
|
||||
addr = (unsigned long)vm->addr;
|
||||
if (addr < next)
|
||||
@ -961,8 +961,8 @@ void __init sanity_check_meminfo(void)
|
||||
* Check whether this memory bank would partially overlap
|
||||
* the vmalloc area.
|
||||
*/
|
||||
if (__va(bank->start + bank->size) > vmalloc_min ||
|
||||
__va(bank->start + bank->size) < __va(bank->start)) {
|
||||
if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
|
||||
__va(bank->start + bank->size - 1) <= __va(bank->start)) {
|
||||
unsigned long newsize = vmalloc_min - __va(bank->start);
|
||||
printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
|
||||
"to -%.8llx (vmalloc region overlap).\n",
|
||||
|
@ -189,6 +189,7 @@ struct omap_dm_timer *omap_dm_timer_request(void)
|
||||
timer->reserved = 1;
|
||||
break;
|
||||
}
|
||||
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
||||
|
||||
if (timer) {
|
||||
ret = omap_dm_timer_prepare(timer);
|
||||
@ -197,7 +198,6 @@ struct omap_dm_timer *omap_dm_timer_request(void)
|
||||
timer = NULL;
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
||||
|
||||
if (!timer)
|
||||
pr_debug("%s: timer request failed!\n", __func__);
|
||||
@ -220,6 +220,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
|
||||
break;
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
||||
|
||||
if (timer) {
|
||||
ret = omap_dm_timer_prepare(timer);
|
||||
@ -228,7 +229,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
|
||||
timer = NULL;
|
||||
}
|
||||
}
|
||||
spin_unlock_irqrestore(&dm_timer_lock, flags);
|
||||
|
||||
if (!timer)
|
||||
pr_debug("%s: timer%d request failed!\n", __func__, id);
|
||||
@ -258,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
|
||||
|
||||
void omap_dm_timer_disable(struct omap_dm_timer *timer)
|
||||
{
|
||||
pm_runtime_put(&timer->pdev->dev);
|
||||
pm_runtime_put_sync(&timer->pdev->dev);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
|
||||
|
||||
|
@ -372,7 +372,8 @@ IS_OMAP_TYPE(3430, 0x3430)
|
||||
#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
|
||||
cpu_is_omap16xx())
|
||||
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
|
||||
cpu_is_omap44xx() || soc_is_omap54xx())
|
||||
cpu_is_omap44xx() || soc_is_omap54xx() || \
|
||||
soc_is_am33xx())
|
||||
|
||||
/* Various silicon revisions for omap2 */
|
||||
#define OMAP242X_CLASS 0x24200024
|
||||
|
@ -108,4 +108,13 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AM33XX
|
||||
# ifdef OMAP_NAME
|
||||
# undef MULTI_OMAP2
|
||||
# define MULTI_OMAP2
|
||||
# else
|
||||
# define OMAP_NAME am33xx
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __PLAT_OMAP_MULTI_H */
|
||||
|
@ -110,7 +110,7 @@ static inline void flush(void)
|
||||
_DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
|
||||
AM33XXUART##p)
|
||||
|
||||
static inline void __arch_decomp_setup(unsigned long arch_id)
|
||||
static inline void arch_decomp_setup(void)
|
||||
{
|
||||
int port = 0;
|
||||
|
||||
@ -198,8 +198,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
|
||||
} while (0);
|
||||
}
|
||||
|
||||
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
|
@ -68,6 +68,7 @@
|
||||
|
||||
static unsigned long omap_sram_start;
|
||||
static void __iomem *omap_sram_base;
|
||||
static unsigned long omap_sram_skip;
|
||||
static unsigned long omap_sram_size;
|
||||
static void __iomem *omap_sram_ceil;
|
||||
|
||||
@ -106,6 +107,7 @@ static int is_sram_locked(void)
|
||||
*/
|
||||
static void __init omap_detect_sram(void)
|
||||
{
|
||||
omap_sram_skip = SRAM_BOOTLOADER_SZ;
|
||||
if (cpu_class_is_omap2()) {
|
||||
if (is_sram_locked()) {
|
||||
if (cpu_is_omap34xx()) {
|
||||
@ -113,6 +115,7 @@ static void __init omap_detect_sram(void)
|
||||
if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
|
||||
(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
|
||||
omap_sram_size = 0x7000; /* 28K */
|
||||
omap_sram_skip += SZ_16K;
|
||||
} else {
|
||||
omap_sram_size = 0x8000; /* 32K */
|
||||
}
|
||||
@ -175,8 +178,10 @@ static void __init omap_map_sram(void)
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_OMAP4_ERRATA_I688
|
||||
if (cpu_is_omap44xx()) {
|
||||
omap_sram_start += PAGE_SIZE;
|
||||
omap_sram_size -= SZ_16K;
|
||||
}
|
||||
#endif
|
||||
if (cpu_is_omap34xx()) {
|
||||
/*
|
||||
@ -203,8 +208,8 @@ static void __init omap_map_sram(void)
|
||||
* Looks like we need to preserve some bootloader code at the
|
||||
* beginning of SRAM for jumping to flash for reboot to work...
|
||||
*/
|
||||
memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
|
||||
omap_sram_size - SRAM_BOOTLOADER_SZ);
|
||||
memset_io(omap_sram_base + omap_sram_skip, 0,
|
||||
omap_sram_size - omap_sram_skip);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -218,7 +223,7 @@ void *omap_sram_push_address(unsigned long size)
|
||||
{
|
||||
unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
|
||||
|
||||
available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
|
||||
available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
|
||||
|
||||
if (size > available) {
|
||||
pr_err("Not enough space in SRAM\n");
|
||||
|
@ -291,10 +291,12 @@ static struct platform_device orion_ge00 = {
|
||||
void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
|
||||
unsigned long mapbase,
|
||||
unsigned long irq,
|
||||
unsigned long irq_err)
|
||||
unsigned long irq_err,
|
||||
unsigned int tx_csum_limit)
|
||||
{
|
||||
fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
|
||||
mapbase + 0x2000, SZ_16K - 1, irq_err);
|
||||
orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
|
||||
ge_complete(&orion_ge00_shared_data,
|
||||
orion_ge00_resources, irq, &orion_ge00_shared,
|
||||
eth_data, &orion_ge00);
|
||||
@ -343,10 +345,12 @@ static struct platform_device orion_ge01 = {
|
||||
void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
|
||||
unsigned long mapbase,
|
||||
unsigned long irq,
|
||||
unsigned long irq_err)
|
||||
unsigned long irq_err,
|
||||
unsigned int tx_csum_limit)
|
||||
{
|
||||
fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
|
||||
mapbase + 0x2000, SZ_16K - 1, irq_err);
|
||||
orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
|
||||
ge_complete(&orion_ge01_shared_data,
|
||||
orion_ge01_resources, irq, &orion_ge01_shared,
|
||||
eth_data, &orion_ge01);
|
||||
|
@ -39,12 +39,14 @@ void __init orion_rtc_init(unsigned long mapbase,
|
||||
void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
|
||||
unsigned long mapbase,
|
||||
unsigned long irq,
|
||||
unsigned long irq_err);
|
||||
unsigned long irq_err,
|
||||
unsigned int tx_csum_limit);
|
||||
|
||||
void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
|
||||
unsigned long mapbase,
|
||||
unsigned long irq,
|
||||
unsigned long irq_err);
|
||||
unsigned long irq_err,
|
||||
unsigned int tx_csum_limit);
|
||||
|
||||
void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
|
||||
unsigned long mapbase,
|
||||
|
@ -430,7 +430,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
|
||||
* when necessary.
|
||||
*/
|
||||
|
||||
int s3c2410_dma_enqueue(unsigned int channel, void *id,
|
||||
int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
|
||||
dma_addr_t data, int size)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
@ -32,6 +32,8 @@
|
||||
#include <linux/platform_data/s3c-hsudc.h>
|
||||
#include <linux/platform_data/s3c-hsotg.h>
|
||||
|
||||
#include <media/s5p_hdmi.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/pmu.h>
|
||||
#include <asm/mach/arch.h>
|
||||
@ -748,7 +750,8 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
|
||||
if (!pd) {
|
||||
pd = &default_i2c_data;
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
if (soc_is_exynos4210() ||
|
||||
soc_is_exynos4212() || soc_is_exynos4412())
|
||||
pd->bus_num = 8;
|
||||
else if (soc_is_s5pv210())
|
||||
pd->bus_num = 3;
|
||||
@ -759,6 +762,30 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
|
||||
npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
|
||||
&s5p_device_i2c_hdmiphy);
|
||||
}
|
||||
|
||||
struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
|
||||
|
||||
void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
|
||||
struct i2c_board_info *mhl_info, int mhl_bus)
|
||||
{
|
||||
struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
|
||||
|
||||
if (soc_is_exynos4210() ||
|
||||
soc_is_exynos4212() || soc_is_exynos4412())
|
||||
pd->hdmiphy_bus = 8;
|
||||
else if (soc_is_s5pv210())
|
||||
pd->hdmiphy_bus = 3;
|
||||
else
|
||||
pd->hdmiphy_bus = 0;
|
||||
|
||||
pd->hdmiphy_info = hdmiphy_info;
|
||||
pd->mhl_info = mhl_info;
|
||||
pd->mhl_bus = mhl_bus;
|
||||
|
||||
s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
|
||||
&s5p_device_hdmi);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
|
||||
|
||||
/* I2S */
|
||||
|
16
arch/arm/plat-samsung/include/plat/hdmi.h
Normal file
16
arch/arm/plat-samsung/include/plat/hdmi.h
Normal file
@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Samsung Electronics Co.Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_SAMSUNG_HDMI_H
|
||||
#define __PLAT_SAMSUNG_HDMI_H __FILE__
|
||||
|
||||
extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
|
||||
struct i2c_board_info *mhl_info, int mhl_bus);
|
||||
|
||||
#endif /* __PLAT_SAMSUNG_HDMI_H */
|
@ -74,7 +74,7 @@ unsigned char pm_uart_udivslot;
|
||||
|
||||
#ifdef CONFIG_SAMSUNG_PM_DEBUG
|
||||
|
||||
struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
|
||||
static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
|
||||
|
||||
static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
|
||||
{
|
||||
|
@ -38,6 +38,7 @@ config BLACKFIN
|
||||
select GENERIC_ATOMIC64
|
||||
select GENERIC_IRQ_PROBE
|
||||
select IRQ_PER_CPU if SMP
|
||||
select USE_GENERIC_SMP_HELPERS if SMP
|
||||
select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
|
||||
select GENERIC_SMP_IDLE_THREAD
|
||||
select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
|
||||
|
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Reference in New Issue
Block a user