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https://github.com/edk2-porting/linux-next.git
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Detect the MIPS R2 vectored interrupt, external interrupt controller
options and the precense of the MT ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
699dbc90e8
commit
8f40611d2b
@ -501,6 +501,12 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
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c->ases |= MIPS_ASE_SMARTMIPS;
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if (config3 & MIPS_CONF3_DSP)
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c->ases |= MIPS_ASE_DSP;
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if (config3 & MIPS_CONF3_VINT)
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c->options |= MIPS_CPU_VINT;
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if (config3 & MIPS_CONF3_VEIC)
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c->options |= MIPS_CPU_VEIC;
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if (config3 & MIPS_CONF3_MT)
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c->ases |= MIPS_ASE_MIPSMT;
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return config3 & MIPS_CONF_M;
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}
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@ -109,6 +109,14 @@
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#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
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#endif
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#ifdef CONFIG_MIPS_MT
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#ifndef cpu_has_mipsmt
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# define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
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#endif
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#else
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# define cpu_has_mipsmt 0
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#endif
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#ifdef CONFIG_32BIT
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# ifndef cpu_has_nofpuex
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# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
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@ -145,6 +153,22 @@
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# endif
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#endif
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#ifdef CONFIG_CPU_MIPSR2
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# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
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# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
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# else
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# define cpu_has_vint 0
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# endif
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# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
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# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
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# else
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# define cpu_has_veic 0
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# endif
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#else
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# define cpu_has_vint 0
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# define cpu_has_veic 0
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#endif
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#ifndef cpu_has_subset_pcaches
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#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
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#endif
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@ -227,6 +227,8 @@
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#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
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#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
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#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
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#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
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#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
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/*
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* CPU ASE encodings
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@ -236,5 +238,7 @@
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#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
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#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
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#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
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#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
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#endif /* _ASM_CPU_H */
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@ -175,8 +175,8 @@ static inline unsigned int dvpe(void)
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" .set noreorder \n"
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" .set noat \n"
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" .set mips32r2 \n"
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" move $1, %0 \n"
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" .word 0x41610001 # dvpe $1 \n"
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" move %0, $1 \n"
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" ehb \n"
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" .set pop \n"
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: "=r" (res));
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@ -214,12 +214,13 @@ static inline unsigned int dmt(void)
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int res;
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__asm__ __volatile__(
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" .set noreorder \n"
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" .set push \n"
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" .set mips32r2 \n"
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" dmt %0 \n"
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" .set noat \n"
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" .word 0x41610BC1 # dmt $1 \n"
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" ehb \n"
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" .set mips0 \n"
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" .set reorder \n"
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" move %0, $1 \n"
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" .set pop \n"
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: "=r" (res));
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instruction_hazard();
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@ -251,7 +252,10 @@ static inline void emt(int previous)
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static inline void ehb(void)
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{
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__asm__ __volatile__("ehb");
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__asm__ __volatile__(
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" .set mips32r2 \n"
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" ehb \n"
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" .set mips0 \n");
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}
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#define mftc0(rt,sel) \
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@ -259,10 +263,14 @@ static inline void ehb(void)
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unsigned long __res; \
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\
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__asm__ __volatile__( \
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" .set noat\n\t" \
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" mftc0\t%0," #rt ", " #sel "\n\t" \
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" .set at\n\t" \
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: "=r" (__res)); \
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" .set push \n" \
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" .set mips32r2 \n" \
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" .set noat \n" \
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" # mftc0 $1, $" #rt ", " #sel " \n" \
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" .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
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" move %0, $1 \n" \
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" .set pop \n" \
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: "=r" (__res)); \
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\
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__res; \
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})
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@ -272,9 +280,10 @@ static inline void ehb(void)
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unsigned long __res; \
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\
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__asm__ __volatile__( \
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" .set noat \n" \
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" .set push \n" \
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" .set mips32r2 \n" \
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" mftgpr %0," #rt " \n" \
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" .set at \n" \
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" .set pop \n" \
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: "=r" (__res)); \
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\
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__res; \
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@ -294,17 +303,30 @@ static inline void ehb(void)
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})
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#define mttgpr(rd,v) \
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({ \
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do { \
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__asm__ __volatile__( \
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"mttgpr %0," #rd \
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" .set push \n" \
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" .set mips32r2 \n" \
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" .set noat \n" \
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" move $1, %0 \n" \
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" # mttgpr $1, " #rd " \n" \
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" .word 0x41810020 | (" #rd " << 11) \n" \
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" .set pop \n" \
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: : "r" (v)); \
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})
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} while (0)
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#define mttc0(rd,sel,v) \
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({ \
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__asm__ __volatile__( \
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"mttc0\t %0," #rd ", " #sel \
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: : "r" (v)); \
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" .set push \n" \
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" .set mips32r2 \n" \
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" .set noat \n" \
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" move $1, %0 \n" \
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" # mttc0 %0," #rd ", " #sel " \n" \
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" .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
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" .set pop \n" \
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: \
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: "r" (v)); \
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})
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@ -324,42 +346,42 @@ do { \
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/* you *must* set the target tc (settc) before trying to use these */
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#define read_vpe_c0_vpecontrol() mftc0($1, 1)
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#define write_vpe_c0_vpecontrol(val) mttc0($1, 1, val)
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#define read_vpe_c0_vpeconf0() mftc0($1, 2)
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#define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val)
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#define read_vpe_c0_status() mftc0($12, 0)
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#define write_vpe_c0_status(val) mttc0($12, 0, val)
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#define read_vpe_c0_cause() mftc0($13, 0)
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#define write_vpe_c0_cause(val) mttc0($13, 0, val)
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#define read_vpe_c0_config() mftc0($16, 0)
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#define write_vpe_c0_config(val) mttc0($16, 0, val)
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#define read_vpe_c0_config1() mftc0($16, 1)
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#define write_vpe_c0_config1(val) mttc0($16, 1, val)
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#define read_vpe_c0_config7() mftc0($16, 7)
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#define write_vpe_c0_config7(val) mttc0($16, 7, val)
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#define read_vpe_c0_ebase() mftc0($15,1)
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#define write_vpe_c0_ebase(val) mttc0($15, 1, val)
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#define write_vpe_c0_compare(val) mttc0($11, 0, val)
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#define read_vpe_c0_vpecontrol() mftc0(1, 1)
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#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
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#define read_vpe_c0_vpeconf0() mftc0(1, 2)
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#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
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#define read_vpe_c0_status() mftc0(12, 0)
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#define write_vpe_c0_status(val) mttc0(12, 0, val)
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#define read_vpe_c0_cause() mftc0(13, 0)
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#define write_vpe_c0_cause(val) mttc0(13, 0, val)
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#define read_vpe_c0_config() mftc0(16, 0)
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#define write_vpe_c0_config(val) mttc0(16, 0, val)
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#define read_vpe_c0_config1() mftc0(16, 1)
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#define write_vpe_c0_config1(val) mttc0(16, 1, val)
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#define read_vpe_c0_config7() mftc0(16, 7)
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#define write_vpe_c0_config7(val) mttc0(16, 7, val)
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#define read_vpe_c0_ebase() mftc0(15,1)
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#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
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#define write_vpe_c0_compare(val) mttc0(11, 0, val)
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/* TC */
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#define read_tc_c0_tcstatus() mftc0($2, 1)
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#define write_tc_c0_tcstatus(val) mttc0($2,1,val)
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#define read_tc_c0_tcbind() mftc0($2, 2)
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#define write_tc_c0_tcbind(val) mttc0($2,2,val)
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#define read_tc_c0_tcrestart() mftc0($2, 3)
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#define write_tc_c0_tcrestart(val) mttc0($2,3,val)
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#define read_tc_c0_tchalt() mftc0($2, 4)
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#define write_tc_c0_tchalt(val) mttc0($2,4,val)
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#define read_tc_c0_tccontext() mftc0($2, 5)
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#define write_tc_c0_tccontext(val) mttc0($2,5,val)
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#define read_tc_c0_tcstatus() mftc0(2, 1)
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#define write_tc_c0_tcstatus(val) mttc0(2,1,val)
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#define read_tc_c0_tcbind() mftc0(2, 2)
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#define write_tc_c0_tcbind(val) mttc0(2,2,val)
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#define read_tc_c0_tcrestart() mftc0(2, 3)
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#define write_tc_c0_tcrestart(val) mttc0(2,3,val)
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#define read_tc_c0_tchalt() mftc0(2, 4)
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#define write_tc_c0_tchalt(val) mttc0(2,4,val)
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#define read_tc_c0_tccontext() mftc0(2, 5)
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#define write_tc_c0_tccontext(val) mttc0(2,5,val)
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/* GPR */
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#define read_tc_gpr_sp() mftgpr($29)
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#define write_tc_gpr_sp(val) mttgpr($29, val)
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#define read_tc_gpr_gp() mftgpr($28)
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#define write_tc_gpr_gp(val) mttgpr($28, val)
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#define read_tc_gpr_sp() mftgpr(29)
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#define write_tc_gpr_sp(val) mttgpr(29, val)
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#define read_tc_gpr_gp() mftgpr(28)
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#define write_tc_gpr_gp(val) mttgpr(28, val)
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#endif /* Not __ASSEMBLY__ */
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@ -528,6 +528,7 @@
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#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
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#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
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#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
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#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
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#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
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#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
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