mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 12:43:55 +08:00
drm/nouveau/dp: remove last bits of VBIOS parsing from DRM code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
6c8e4633d3
commit
8f2abc2586
@ -26,6 +26,12 @@ struct nv50_disp_priv {
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int (*power)(struct nv50_disp_priv *, int sor, u32 data);
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int (*hda_eld)(struct nv50_disp_priv *, int sor, u8 *, u32);
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int (*hdmi)(struct nv50_disp_priv *, int head, int sor, u32);
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int (*dp_train_init)(struct nv50_disp_priv *, int sor, int link,
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int head, u16 type, u16 mask, u32 data,
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struct dcb_output *);
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int (*dp_train_fini)(struct nv50_disp_priv *, int sor, int link,
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int head, u16 type, u16 mask, u32 data,
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struct dcb_output *);
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int (*dp_train)(struct nv50_disp_priv *, int sor, int link,
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u16 type, u16 mask, u32 data,
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struct dcb_output *);
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@ -57,6 +63,10 @@ int nvd0_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);
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int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);
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int nv50_sor_power(struct nv50_disp_priv *, int, u32);
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int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,
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u32, struct dcb_output *);
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int nv94_sor_dp_train_fini(struct nv50_disp_priv *, int, int, int, u16, u16,
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u32, struct dcb_output *);
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int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
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struct dcb_output *);
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int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
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@ -87,6 +87,8 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->sor.power = nv50_sor_power;
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priv->sor.hdmi = nv84_hdmi_ctrl;
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priv->sor.dp_train = nv94_sor_dp_train;
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priv->sor.dp_train_init = nv94_sor_dp_train_init;
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priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
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priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
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priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
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@ -89,6 +89,8 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->sor.hda_eld = nva3_hda_eld;
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priv->sor.hdmi = nva3_hdmi_ctrl;
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priv->sor.dp_train = nv94_sor_dp_train;
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priv->sor.dp_train_init = nv94_sor_dp_train_init;
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priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
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priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
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priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
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@ -951,6 +951,8 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->sor.hda_eld = nvd0_hda_eld;
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priv->sor.hdmi = nvd0_hdmi_ctrl;
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priv->sor.dp_train = nvd0_sor_dp_train;
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priv->sor.dp_train_init = nv94_sor_dp_train_init;
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priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
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priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;
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priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;
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@ -72,6 +72,8 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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priv->sor.hda_eld = nvd0_hda_eld;
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priv->sor.hdmi = nvd0_hdmi_ctrl;
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priv->sor.dp_train = nvd0_sor_dp_train;
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priv->sor.dp_train_init = nv94_sor_dp_train_init;
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priv->sor.dp_train_fini = nv94_sor_dp_train_fini;
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priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl;
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priv->sor.dp_drvctl = nvd0_sor_dp_drvctl;
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@ -80,7 +80,19 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
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ret = 0;
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break;
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case NV94_DISP_SOR_DP_TRAIN:
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ret = priv->sor.dp_train(priv, or, link, type, mask, data, &outp);
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switch (data & NV94_DISP_SOR_DP_TRAIN_OP) {
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case NV94_DISP_SOR_DP_TRAIN_OP_PATTERN:
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ret = priv->sor.dp_train(priv, or, link, type, mask, data, &outp);
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break;
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case NV94_DISP_SOR_DP_TRAIN_OP_INIT:
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ret = priv->sor.dp_train_init(priv, or, link, head, type, mask, data, &outp);
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break;
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case NV94_DISP_SOR_DP_TRAIN_OP_FINI:
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ret = priv->sor.dp_train_fini(priv, or, link, head, type, mask, data, &outp);
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break;
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default:
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break;
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}
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break;
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case NV94_DISP_SOR_DP_LNKCTL:
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ret = priv->sor.dp_lnkctl(priv, or, link, head, type, mask, data, &outp);
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@ -42,6 +42,64 @@ nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
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return nv94[lane];
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}
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int
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nv94_sor_dp_train_init(struct nv50_disp_priv *priv, int or, int link, int head,
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u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
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{
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struct nouveau_bios *bios = nouveau_bios(priv);
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struct nvbios_dpout info;
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u8 ver, hdr, cnt, len;
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u16 outp;
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outp = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &info);
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if (outp) {
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struct nvbios_init init = {
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.subdev = nv_subdev(priv),
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.bios = bios,
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.outp = dcbo,
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.crtc = head,
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.execute = 1,
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};
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if (data & NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON)
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init.offset = info.script[2];
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else
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init.offset = info.script[3];
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nvbios_exec(&init);
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init.offset = info.script[0];
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nvbios_exec(&init);
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}
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return 0;
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}
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int
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nv94_sor_dp_train_fini(struct nv50_disp_priv *priv, int or, int link, int head,
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u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
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{
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struct nouveau_bios *bios = nouveau_bios(priv);
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struct nvbios_dpout info;
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u8 ver, hdr, cnt, len;
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u16 outp;
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outp = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &info);
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if (outp) {
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struct nvbios_init init = {
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.subdev = nv_subdev(priv),
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.bios = bios,
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.offset = info.script[1],
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.outp = dcbo,
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.crtc = head,
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.execute = 1,
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};
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nvbios_exec(&init);
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}
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return 0;
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}
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int
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nv94_sor_dp_train(struct nv50_disp_priv *priv, int or, int link,
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u16 type, u16 mask, u32 data, struct dcb_output *info)
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@ -191,6 +191,13 @@ struct nve0_channel_ind_class {
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#define NV50_DISP_SOR_LVDS_SCRIPT 0x00013000
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#define NV50_DISP_SOR_LVDS_SCRIPT_ID 0x0000ffff
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#define NV94_DISP_SOR_DP_TRAIN 0x00016000
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#define NV94_DISP_SOR_DP_TRAIN_OP 0xf0000000
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#define NV94_DISP_SOR_DP_TRAIN_OP_PATTERN 0x00000000
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#define NV94_DISP_SOR_DP_TRAIN_OP_INIT 0x10000000
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#define NV94_DISP_SOR_DP_TRAIN_OP_FINI 0x20000000
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#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD 0x00000001
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#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF 0x00000000
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#define NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON 0x00000001
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#define NV94_DISP_SOR_DP_TRAIN_PATTERN 0x00000003
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#define NV94_DISP_SOR_DP_TRAIN_PATTERN_DISABLED 0x00000000
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#define NV94_DISP_SOR_DP_LNKCTL 0x00016040
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@ -624,34 +624,6 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
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return 0;
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}
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/* BIT 'U'/'d' table encoder subtables have hashes matching them to
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* a particular set of encoders.
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*
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* This function returns true if a particular DCB entry matches.
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*/
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bool
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bios_encoder_match(struct dcb_output *dcb, u32 hash)
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{
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if ((hash & 0x000000f0) != (dcb->location << 4))
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return false;
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if ((hash & 0x0000000f) != dcb->type)
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return false;
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if (!(hash & (dcb->or << 16)))
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return false;
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switch (dcb->type) {
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case DCB_OUTPUT_TMDS:
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case DCB_OUTPUT_LVDS:
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case DCB_OUTPUT_DP:
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if (hash & 0x00c00000) {
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if (!(hash & (dcb->sorconf.link << 22)))
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return false;
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}
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default:
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return true;
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}
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}
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int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head, int pxclk)
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{
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/*
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@ -187,6 +187,5 @@ int run_tmds_table(struct drm_device *, struct dcb_output *,
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int head, int pxclk);
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int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
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enum LVDS_script, int pxclk);
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bool bios_encoder_match(struct dcb_output *, u32 hash);
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#endif
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@ -35,51 +35,6 @@
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#include <subdev/gpio.h>
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#include <subdev/i2c.h>
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u8 *
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nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct bit_entry d;
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u8 *table;
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int i;
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if (bit_table(dev, 'd', &d)) {
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NV_ERROR(drm, "BIT 'd' table not found\n");
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return NULL;
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}
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if (d.version != 1) {
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NV_ERROR(drm, "BIT 'd' table version %d unknown\n", d.version);
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return NULL;
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}
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table = ROMPTR(dev, d.data[0]);
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if (!table) {
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NV_ERROR(drm, "displayport table pointer invalid\n");
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return NULL;
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}
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switch (table[0]) {
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case 0x20:
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case 0x21:
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case 0x30:
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case 0x40:
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break;
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default:
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NV_ERROR(drm, "displayport table 0x%02x unknown\n", table[0]);
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return NULL;
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}
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for (i = 0; i < table[3]; i++) {
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*entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
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if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
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return table;
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}
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NV_ERROR(drm, "displayport encoder table not found\n");
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return NULL;
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}
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/******************************************************************************
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* link training
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*****************************************************************************/
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@ -250,54 +205,27 @@ dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
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}
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static void
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dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
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dp_link_train_init(struct drm_device *dev, struct dp_state *dp, bool spread)
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{
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u16 script = 0x0000;
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u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
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if (table) {
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if (table[0] >= 0x20 && table[0] <= 0x30) {
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if (enable) script = ROM16(entry[12]);
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else script = ROM16(entry[14]);
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} else
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if (table[0] == 0x40) {
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if (enable) script = ROM16(entry[11]);
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else script = ROM16(entry[13]);
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}
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}
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struct dcb_output *dcb = dp->dcb;
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const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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const u32 moff = (dp->crtc << 3) | (link << 2) | or;
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nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
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}
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static void
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dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
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{
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u16 script = 0x0000;
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u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
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if (table) {
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if (table[0] >= 0x20 && table[0] <= 0x30)
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script = ROM16(entry[6]);
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else
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if (table[0] == 0x40)
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script = ROM16(entry[5]);
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}
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nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
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nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, (spread ?
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NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON :
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NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF) |
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NV94_DISP_SOR_DP_TRAIN_OP_INIT);
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}
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static void
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dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
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{
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u16 script = 0x0000;
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u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
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if (table) {
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if (table[0] >= 0x20 && table[0] <= 0x30)
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script = ROM16(entry[8]);
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else
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if (table[0] == 0x40)
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script = ROM16(entry[7]);
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}
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struct dcb_output *dcb = dp->dcb;
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const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
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const u32 moff = (dp->crtc << 3) | (link << 2) | or;
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nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
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nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff,
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NV94_DISP_SOR_DP_TRAIN_OP_FINI);
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}
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static bool
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@ -334,11 +262,8 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
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*/
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gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);
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/* enable down-spreading, if possible */
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dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
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/* execute pre-train script from vbios */
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dp_link_train_init(dev, &dp);
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/* enable down-spreading and execute pre-train script from vbios */
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dp_link_train_init(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
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/* start off at highest link rate supported by encoder and display */
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while (*link_bw > nv_encoder->dp.link_bw)
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@ -94,7 +94,6 @@ get_slave_funcs(struct drm_encoder *enc)
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bool nouveau_dp_detect(struct drm_encoder *);
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void nouveau_dp_dpms(struct drm_encoder *, int mode, u32 datarate,
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struct nouveau_object *);
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u8 *nouveau_dp_bios_data(struct drm_device *, struct dcb_output *, u8 **);
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struct nouveau_connector *
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nouveau_encoder_connector_get(struct nouveau_encoder *encoder);
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