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w1: Disable irqs during 1-wire bus operations, extend 1-wire reset pulse
This patch offers the possibility to disables irqs during w1_write_bit() and w1_reset_bus() operations as timing requirements are very strict for the 1-wire bus protocol. Per default interrupts are enabled but can be disabled via the module parameter "w1_disable_irqs". Extend 1-wire reset pulse length from 480us to 500us as 480us is the minimum requirement for the 1-wire reset/presence pulse. Signed-off-by: Markus Franke <franm@hrz.tu-chemnitz.de> Acked-by: Evgeniy Polyakov <zbr@ioremap.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -31,6 +31,9 @@
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static int w1_delay_parm = 1;
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module_param_named(delay_coef, w1_delay_parm, int, 0);
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static int w1_disable_irqs = 0;
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module_param_named(disable_irqs, w1_disable_irqs, int, 0);
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static u8 w1_crc8_table[] = {
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0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
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157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
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@ -79,6 +82,10 @@ static u8 w1_touch_bit(struct w1_master *dev, int bit)
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*/
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static void w1_write_bit(struct w1_master *dev, int bit)
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{
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unsigned long flags = 0;
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if(w1_disable_irqs) local_irq_save(flags);
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if (bit) {
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dev->bus_master->write_bit(dev->bus_master->data, 0);
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w1_delay(6);
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@ -90,6 +97,8 @@ static void w1_write_bit(struct w1_master *dev, int bit)
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dev->bus_master->write_bit(dev->bus_master->data, 1);
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w1_delay(10);
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}
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if(w1_disable_irqs) local_irq_restore(flags);
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}
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/**
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@ -158,7 +167,7 @@ EXPORT_SYMBOL_GPL(w1_write_8);
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static u8 w1_read_bit(struct w1_master *dev)
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{
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int result;
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unsigned long flags;
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unsigned long flags = 0;
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/* sample timing is critical here */
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local_irq_save(flags);
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@ -318,6 +327,9 @@ EXPORT_SYMBOL_GPL(w1_read_block);
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int w1_reset_bus(struct w1_master *dev)
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{
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int result;
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unsigned long flags = 0;
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if(w1_disable_irqs) local_irq_save(flags);
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if (dev->bus_master->reset_bus)
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result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
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@ -330,19 +342,21 @@ int w1_reset_bus(struct w1_master *dev)
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* cpu for such a short amount of time AND get it back in
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* the maximum amount of time.
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*/
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w1_delay(480);
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w1_delay(500);
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dev->bus_master->write_bit(dev->bus_master->data, 1);
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w1_delay(70);
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result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
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/* minmum 70 (above) + 410 = 480 us
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/* minmum 70 (above) + 430 = 500 us
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* There aren't any timing requirements between a reset and
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* the following transactions. Sleeping is safe here.
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*/
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/* w1_delay(410); min required time */
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/* w1_delay(430); min required time */
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msleep(1);
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}
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if(w1_disable_irqs) local_irq_restore(flags);
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return result;
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}
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EXPORT_SYMBOL_GPL(w1_reset_bus);
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