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scsi: ufs: dt-bindings: add document for hisi-ufs

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add ufs node document for Hisilicon.

Signed-off-by: Li Wei <liwei213@huawei.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
liwei 2018-07-17 17:36:57 +08:00 committed by Martin K. Petersen
parent 8111b5e334
commit 8ee94ec065
2 changed files with 48 additions and 3 deletions
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41
Documentation/devicetree/bindings/ufs/ufs-hisi.txt Normal file
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@ -0,0 +1,41 @@
* Hisilicon Universal Flash Storage (UFS) Host Controller
UFS nodes are defined to describe on-chip UFS hardware macro.
Each UFS Host Controller should have its own node.
Required properties:
- compatible : compatible list, contains one of the following -
"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs
host controller present on Hi36xx chipset.
- reg : should contain UFS register address space & UFS SYS CTRL register address,
- interrupt-parent : interrupt device
- interrupts : interrupt number
- clocks : List of phandle and clock specifier pairs
- clock-names : List of clock input name strings sorted in the same
order as the clocks property. "ref_clk", "phy_clk" is optional
- freq-table-hz : Array of <min max> operating frequencies stored in the same
order as the clocks property. If this property is not
defined or a value in the array is "0" then it is assumed
that the frequency is set by the parent clock or a
fixed rate clock source.
- resets : describe reset node register
- reset-names : reset node register, the "rst" corresponds to reset the whole UFS IP.
Example:
ufs: ufs@ff3b0000 {
compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
/* 0: HCI standard */
/* 1: UFS SYS CTRL */
reg = <0x0 0xff3b0000 0x0 0x1000>,
<0x0 0xff3b1000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
clock-names = "ref_clk", "phy_clk";
freq-table-hz = <0 0>, <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
};

10
Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
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@ -41,6 +41,8 @@ Optional properties:
-lanes-per-direction : number of lanes available per direction - either 1 or 2. -lanes-per-direction : number of lanes available per direction - either 1 or 2.
Note that it is assume same number of lanes is used both Note that it is assume same number of lanes is used both
directions at once. If not specified, default is 2 lanes per direction. directions at once. If not specified, default is 2 lanes per direction.
- resets : reset node register
- reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
Note: If above properties are not defined it can be assumed that the supply Note: If above properties are not defined it can be assumed that the supply
regulators or clocks are always on. regulators or clocks are always on.
@ -61,9 +63,11 @@ Example:
vccq-max-microamp = 200000; vccq-max-microamp = 200000;
vccq2-max-microamp = 200000; vccq2-max-microamp = 200000;
clocks = <&core 0>, <&ref 0>, <&iface 0>; clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
clock-names = "core_clk", "ref_clk", "iface_clk"; clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
freq-table-hz = <100000000 200000000>, <0 0>, <0 0>; freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
resets = <&reset 0 1>;
reset-names = "rst";
phys = <&ufsphy1>; phys = <&ufsphy1>;
phy-names = "ufsphy"; phy-names = "ufsphy";
}; };