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https://github.com/edk2-porting/linux-next.git
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drm/nouveau/ce/gp100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
e8ff979492
commit
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@ -131,6 +131,7 @@
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#define FERMI_DMA 0x000090b5
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#define KEPLER_DMA_COPY_A 0x0000a0b5
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#define MAXWELL_DMA_COPY_A 0x0000b0b5
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#define PASCAL_DMA_COPY_A 0x0000c0b5
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#define FERMI_DECOMPRESS 0x000090b8
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@ -7,4 +7,5 @@ int gf100_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
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int gk104_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
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int gm107_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
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int gm200_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
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int gp100_ce_new(struct nvkm_device *, int, struct nvkm_engine **);
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#endif
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@ -1104,6 +1104,8 @@ nouveau_bo_move_init(struct nouveau_drm *drm)
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struct ttm_mem_reg *, struct ttm_mem_reg *);
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int (*init)(struct nouveau_channel *, u32 handle);
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} _methods[] = {
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{ "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
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{ "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
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{ "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
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{ "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
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{ "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
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@ -3,3 +3,4 @@ nvkm-y += nvkm/engine/ce/gf100.o
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nvkm-y += nvkm/engine/ce/gk104.o
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nvkm-y += nvkm/engine/ce/gm107.o
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nvkm-y += nvkm/engine/ce/gm200.o
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nvkm-y += nvkm/engine/ce/gp100.o
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102
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c
Normal file
102
drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.c
Normal file
@ -0,0 +1,102 @@
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/*
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* Copyright 2015 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include <core/enum.h>
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#include <nvif/class.h>
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static const struct nvkm_enum
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gp100_ce_launcherr_report[] = {
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{ 0x0, "NO_ERR" },
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{ 0x1, "2D_LAYER_EXCEEDS_DEPTH" },
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{ 0x2, "INVALID_ALIGNMENT" },
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{ 0x3, "MEM2MEM_RECT_OUT_OF_BOUNDS" },
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{ 0x4, "SRC_LINE_EXCEEDS_PITCH" },
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{ 0x5, "SRC_LINE_EXCEEDS_NEG_PITCH" },
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{ 0x6, "DST_LINE_EXCEEDS_PITCH" },
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{ 0x7, "DST_LINE_EXCEEDS_NEG_PITCH" },
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{ 0x8, "BAD_SRC_PIXEL_COMP_REF" },
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{ 0x9, "INVALID_VALUE" },
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{ 0xa, "UNUSED_FIELD" },
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{ 0xb, "INVALID_OPERATION" },
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{ 0xc, "NO_RESOURCES" },
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{ 0xd, "INVALID_CONFIG" },
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{}
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};
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static void
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gp100_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base)
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{
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struct nvkm_subdev *subdev = &ce->subdev;
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struct nvkm_device *device = subdev->device;
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u32 stat = nvkm_rd32(device, 0x104418 + base);
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const struct nvkm_enum *en =
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nvkm_enum_find(gp100_ce_launcherr_report, stat & 0x0000000f);
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nvkm_warn(subdev, "LAUNCHERR %08x [%s]\n", stat, en ? en->name : "");
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}
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void
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gp100_ce_intr(struct nvkm_engine *ce)
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{
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const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x80;
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struct nvkm_subdev *subdev = &ce->subdev;
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struct nvkm_device *device = subdev->device;
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u32 mask = nvkm_rd32(device, 0x10440c + base);
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u32 intr = nvkm_rd32(device, 0x104410 + base) & mask;
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if (intr & 0x00000001) { //XXX: guess
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nvkm_warn(subdev, "BLOCKPIPE\n");
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nvkm_wr32(device, 0x104410 + base, 0x00000001);
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intr &= ~0x00000001;
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}
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if (intr & 0x00000002) { //XXX: guess
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nvkm_warn(subdev, "NONBLOCKPIPE\n");
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nvkm_wr32(device, 0x104410 + base, 0x00000002);
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intr &= ~0x00000002;
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}
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if (intr & 0x00000004) {
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gp100_ce_intr_launcherr(ce, base);
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nvkm_wr32(device, 0x104410 + base, 0x00000004);
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intr &= ~0x00000004;
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}
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if (intr) {
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nvkm_warn(subdev, "intr %08x\n", intr);
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nvkm_wr32(device, 0x104410 + base, intr);
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}
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}
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static const struct nvkm_engine_func
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gp100_ce = {
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.intr = gp100_ce_intr,
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.sclass = {
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{ -1, -1, PASCAL_DMA_COPY_A },
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{}
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}
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};
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int
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gp100_ce_new(struct nvkm_device *device, int index,
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struct nvkm_engine **pengine)
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{
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return nvkm_engine_new_(&gp100_ce, device, index, true, pengine);
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}
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@ -2168,6 +2168,12 @@ nv130_chipset = {
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.pci = gp100_pci_new,
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.timer = gk20a_timer_new,
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.top = gk104_top_new,
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.ce[0] = gp100_ce_new,
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.ce[1] = gp100_ce_new,
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.ce[2] = gp100_ce_new,
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.ce[3] = gp100_ce_new,
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.ce[4] = gp100_ce_new,
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.ce[5] = gp100_ce_new,
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.dma = gf119_dma_new,
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.disp = gp100_disp_new,
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.fifo = gp100_fifo_new,
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