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https://github.com/edk2-porting/linux-next.git
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Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: keystone: sci-clk: Fix sci_clk_get clk: meson: mpll: fix mpll0 fractional part ignored clk: samsung: exynos5420: The EPLL rate table corrections clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
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commit
8e7be401f2
@ -22,6 +22,7 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include <linux/bsearch.h>
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#define SCI_CLK_SSC_ENABLE BIT(0)
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#define SCI_CLK_ALLOW_FREQ_CHANGE BIT(1)
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@ -44,6 +45,7 @@ struct sci_clk_data {
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* @dev: Device pointer for the clock provider
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* @clk_data: Clock data
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* @clocks: Clocks array for this device
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* @num_clocks: Total number of clocks for this provider
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*/
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struct sci_clk_provider {
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const struct ti_sci_handle *sci;
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@ -51,6 +53,7 @@ struct sci_clk_provider {
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struct device *dev;
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const struct sci_clk_data *clk_data;
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struct clk_hw **clocks;
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int num_clocks;
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};
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/**
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@ -58,7 +61,6 @@ struct sci_clk_provider {
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* @hw: Hardware clock cookie for common clock framework
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* @dev_id: Device index
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* @clk_id: Clock index
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* @node: Clocks list link
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* @provider: Master clock provider
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* @flags: Flags for the clock
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*/
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@ -66,7 +68,6 @@ struct sci_clk {
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struct clk_hw hw;
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u16 dev_id;
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u8 clk_id;
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struct list_head node;
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struct sci_clk_provider *provider;
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u8 flags;
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};
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@ -367,6 +368,19 @@ err:
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return &sci_clk->hw;
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}
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static int _cmp_sci_clk(const void *a, const void *b)
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{
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const struct sci_clk *ca = a;
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const struct sci_clk *cb = *(struct sci_clk **)b;
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if (ca->dev_id == cb->dev_id && ca->clk_id == cb->clk_id)
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return 0;
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if (ca->dev_id > cb->dev_id ||
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(ca->dev_id == cb->dev_id && ca->clk_id > cb->clk_id))
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return 1;
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return -1;
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}
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/**
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* sci_clk_get - Xlate function for getting clock handles
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* @clkspec: device tree clock specifier
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@ -380,29 +394,22 @@ err:
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static struct clk_hw *sci_clk_get(struct of_phandle_args *clkspec, void *data)
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{
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struct sci_clk_provider *provider = data;
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u16 dev_id;
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u8 clk_id;
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const struct sci_clk_data *clks = provider->clk_data;
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struct clk_hw **clocks = provider->clocks;
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struct sci_clk **clk;
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struct sci_clk key;
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if (clkspec->args_count != 2)
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return ERR_PTR(-EINVAL);
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dev_id = clkspec->args[0];
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clk_id = clkspec->args[1];
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key.dev_id = clkspec->args[0];
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key.clk_id = clkspec->args[1];
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while (clks->num_clks) {
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if (clks->dev == dev_id) {
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if (clk_id >= clks->num_clks)
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return ERR_PTR(-EINVAL);
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clk = bsearch(&key, provider->clocks, provider->num_clocks,
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sizeof(clk), _cmp_sci_clk);
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return clocks[clk_id];
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}
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if (!clk)
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return ERR_PTR(-ENODEV);
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clks++;
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}
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return ERR_PTR(-ENODEV);
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return &(*clk)->hw;
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}
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static int ti_sci_init_clocks(struct sci_clk_provider *p)
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@ -410,18 +417,29 @@ static int ti_sci_init_clocks(struct sci_clk_provider *p)
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const struct sci_clk_data *data = p->clk_data;
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struct clk_hw *hw;
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int i;
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int num_clks = 0;
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while (data->num_clks) {
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p->clocks = devm_kcalloc(p->dev, data->num_clks,
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sizeof(struct sci_clk),
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GFP_KERNEL);
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if (!p->clocks)
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return -ENOMEM;
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num_clks += data->num_clks;
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data++;
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}
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p->num_clocks = num_clks;
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p->clocks = devm_kcalloc(p->dev, num_clks, sizeof(struct sci_clk),
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GFP_KERNEL);
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if (!p->clocks)
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return -ENOMEM;
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num_clks = 0;
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data = p->clk_data;
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while (data->num_clks) {
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for (i = 0; i < data->num_clks; i++) {
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hw = _sci_clk_build(p, data->dev, i);
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if (!IS_ERR(hw)) {
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p->clocks[i] = hw;
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p->clocks[num_clks++] = hw;
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continue;
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}
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@ -161,6 +161,13 @@ static int mpll_set_rate(struct clk_hw *hw,
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reg = PARM_SET(p->width, p->shift, reg, 1);
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writel(reg, mpll->base + p->reg_off);
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p = &mpll->ssen;
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if (p->width != 0) {
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reg = readl(mpll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, 1);
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writel(reg, mpll->base + p->reg_off);
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}
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p = &mpll->n2;
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reg = readl(mpll->base + p->reg_off);
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reg = PARM_SET(p->width, p->shift, reg, n2);
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@ -118,6 +118,7 @@ struct meson_clk_mpll {
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struct parm sdm_en;
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struct parm n2;
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struct parm en;
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struct parm ssen;
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spinlock_t *lock;
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};
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@ -528,6 +528,11 @@ static struct meson_clk_mpll gxbb_mpll0 = {
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.shift = 14,
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.width = 1,
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},
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.ssen = {
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.reg_off = HHI_MPLL_CNTL,
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.shift = 25,
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.width = 1,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "mpll0",
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@ -267,6 +267,11 @@ static struct meson_clk_mpll meson8b_mpll0 = {
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.shift = 14,
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.width = 1,
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},
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.ssen = {
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.reg_off = HHI_MPLL_CNTL,
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.shift = 25,
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.width = 1,
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},
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.lock = &clk_lock,
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.hw.init = &(struct clk_init_data){
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.name = "mpll0",
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@ -1283,16 +1283,16 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
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static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
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PLL_36XX_RATE(600000000U, 100, 2, 1, 0),
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PLL_36XX_RATE(400000000U, 200, 3, 2, 0),
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PLL_36XX_RATE(393216000U, 197, 3, 2, 25690),
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PLL_36XX_RATE(361267200U, 301, 5, 2, 3671),
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PLL_36XX_RATE(393216003U, 197, 3, 2, -25690),
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PLL_36XX_RATE(361267218U, 301, 5, 2, 3671),
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PLL_36XX_RATE(200000000U, 200, 3, 3, 0),
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PLL_36XX_RATE(196608000U, 197, 3, 3, -25690),
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PLL_36XX_RATE(180633600U, 301, 5, 3, 3671),
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PLL_36XX_RATE(131072000U, 131, 3, 3, 4719),
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PLL_36XX_RATE(196608001U, 197, 3, 3, -25690),
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PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
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PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
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PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
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PLL_36XX_RATE(65536000U, 131, 3, 4, 4719),
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PLL_36XX_RATE(49152000U, 197, 3, 5, 25690),
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PLL_36XX_RATE(32768000U, 131, 3, 5, 4719),
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PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
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PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
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PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
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};
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static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
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.hw.init = CLK_HW_INIT_PARENTS("cpu",
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cpu_parents,
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&ccu_mux_ops,
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CLK_IS_CRITICAL),
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CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
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}
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};
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