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https://github.com/edk2-porting/linux-next.git
synced 2024-11-19 08:05:27 +08:00
[AVR32] Clean up OCD register usage
Generate a new set of OCD register definitions in asm/ocd.h and rename __mfdr() and __mtdr() to ocd_read() and ocd_write() respectively. The bitfield definitions are a lot more complete now, and they are entirely based on bit numbers, not masks. This is because OCD registers are frequently accessed from assembly code, where bit numbers are a lot more useful (can be fed directly to sbr, bfins, etc.) Bitfields that consist of more than one bit have two definitions: _START, which indicates the number of the first bit, and _SIZE, which indicates the number of bits. These directly correspond to the parameters taken by the bfextu, bfexts and bfins instructions. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
parent
320516b78b
commit
8dfe8f29cd
@ -270,8 +270,8 @@ syscall_exit_work:
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lsl r3, 1
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sbr r3, 30
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sbr r3, 0
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mtdr DBGREG_BWA2A, r2
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mtdr DBGREG_BWC2A, r3
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mtdr OCD_BWA2A, r2
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mtdr OCD_BWC2A, r3
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rjmp syscall_exit_cont
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@ -521,8 +521,8 @@ fault_exit_work:
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lsl r3, 1
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sbr r3, 30
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sbr r3, 0
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mtdr DBGREG_BWA2A, r2
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mtdr DBGREG_BWC2A, r3
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mtdr OCD_BWA2A, r2
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mtdr OCD_BWC2A, r3
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rjmp fault_resume_user
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/* If we get a debug trap from privileged context we end up here */
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@ -636,9 +636,9 @@ debug_resume_user:
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3: bld r1, TIF_SINGLE_STEP
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brcc debug_restore_all
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mfdr r2, DBGREG_DC
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sbr r2, DC_SS_BIT
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mtdr DBGREG_DC, r2
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mfdr r2, OCD_DC
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sbr r2, OCD_DC_SS_BIT
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mtdr OCD_DC, r2
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rjmp debug_restore_all
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.set rsr_int0, SYSREG_RSR_INT0
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@ -70,9 +70,9 @@ static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
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BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D)));
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dc = __mfdr(DBGREG_DC);
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dc |= DC_SS;
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__mtdr(DBGREG_DC, dc);
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dc = ocd_read(DC);
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dc |= 1 << OCD_DC_SS_BIT;
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ocd_write(DC, dc);
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/*
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* We must run the instruction from its original location
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@ -91,9 +91,9 @@ static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
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pr_debug("resuming execution at PC=%08lx\n", regs->pc);
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dc = __mfdr(DBGREG_DC);
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dc &= ~DC_SS;
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__mtdr(DBGREG_DC, dc);
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dc = ocd_read(DC);
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dc &= ~(1 << OCD_DC_SS_BIT);
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ocd_write(DC, dc);
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*p->addr = BREAKPOINT_INSTRUCTION;
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flush_icache_range((unsigned long)p->addr,
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@ -261,7 +261,7 @@ int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
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int __init arch_init_kprobes(void)
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{
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printk("KPROBES: Enabling monitor mode (MM|DBE)...\n");
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__mtdr(DBGREG_DC, DC_MM | DC_DBE);
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ocd_write(DC, (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
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/* TODO: Register kretprobe trampoline */
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return 0;
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@ -55,8 +55,8 @@ void machine_power_off(void)
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void machine_restart(char *cmd)
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{
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__mtdr(DBGREG_DC, DC_DBE);
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__mtdr(DBGREG_DC, DC_RES);
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ocd_write(DC, (1 << OCD_DC_DBE_BIT));
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ocd_write(DC, (1 << OCD_DC_RES_BIT));
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while (1) ;
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}
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@ -159,7 +159,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
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request, child->pid, addr, data);
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pr_debug("ptrace: Enabling monitor mode...\n");
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__mtdr(DBGREG_DC, __mfdr(DBGREG_DC) | DC_MM | DC_DBE);
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ocd_write(DC, ocd_read(DC) | (1 << OCD_DC_MM_BIT)
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| (1 << OCD_DC_DBE_BIT));
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switch (request) {
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/* Read the word at location addr in the child process */
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@ -240,7 +241,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
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break;
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}
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pr_debug("sys_ptrace returning %d (DC = 0x%08lx)\n", ret, __mfdr(DBGREG_DC));
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pr_debug("sys_ptrace returning %d (DC = 0x%08lx)\n",
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ret, ocd_read(DC));
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return ret;
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}
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@ -276,11 +278,11 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
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unsigned long dc, ds;
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unsigned long die_val;
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ds = __mfdr(DBGREG_DS);
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ds = ocd_read(DS);
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pr_debug("do_debug_priv: pc = %08lx, ds = %08lx\n", regs->pc, ds);
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if (ds & DS_SSS)
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if (ds & (1 << OCD_DS_SSS_BIT))
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die_val = DIE_SSTEP;
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else
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die_val = DIE_BREAKPOINT;
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@ -288,14 +290,14 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
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if (notify_die(die_val, "ptrace", regs, 0, 0, SIGTRAP) == NOTIFY_STOP)
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return;
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if (likely(ds & DS_SSS)) {
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if (likely(ds & (1 << OCD_DS_SSS_BIT))) {
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extern void itlb_miss(void);
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extern void tlb_miss_common(void);
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struct thread_info *ti;
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dc = __mfdr(DBGREG_DC);
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dc &= ~DC_SS;
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__mtdr(DBGREG_DC, dc);
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dc = ocd_read(DC);
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dc &= ~(1 << OCD_DC_SS_BIT);
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ocd_write(DC, dc);
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ti = current_thread_info();
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set_ti_thread_flag(ti, TIF_BREAKPOINT);
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@ -303,8 +305,8 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
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/* The TLB miss handlers don't check thread flags */
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if ((regs->pc >= (unsigned long)&itlb_miss)
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&& (regs->pc <= (unsigned long)&tlb_miss_common)) {
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__mtdr(DBGREG_BWA2A, sysreg_read(RAR_EX));
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__mtdr(DBGREG_BWC2A, 0x40000001 | (get_asid() << 1));
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ocd_write(BWA2A, sysreg_read(RAR_EX));
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ocd_write(BWC2A, 0x40000001 | (get_asid() << 1));
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}
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/*
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@ -329,22 +331,22 @@ asmlinkage void do_debug(struct pt_regs *regs)
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{
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unsigned long dc, ds;
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ds = __mfdr(DBGREG_DS);
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ds = ocd_read(DS);
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pr_debug("do_debug: pc = %08lx, ds = %08lx\n", regs->pc, ds);
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if (test_thread_flag(TIF_BREAKPOINT)) {
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pr_debug("TIF_BREAKPOINT set\n");
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/* We're taking care of it */
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clear_thread_flag(TIF_BREAKPOINT);
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__mtdr(DBGREG_BWC2A, 0);
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ocd_write(BWC2A, 0);
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}
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if (test_thread_flag(TIF_SINGLE_STEP)) {
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pr_debug("TIF_SINGLE_STEP set, ds = 0x%08lx\n", ds);
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if (ds & DS_SSS) {
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dc = __mfdr(DBGREG_DC);
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dc &= ~DC_SS;
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__mtdr(DBGREG_DC, dc);
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if (ds & (1 << OCD_DS_SSS_BIT)) {
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dc = ocd_read(DC);
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dc &= ~(1 << OCD_DC_SS_BIT);
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ocd_write(DC, dc);
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clear_thread_flag(TIF_SINGLE_STEP);
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ptrace_break(current, regs);
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@ -39,7 +39,7 @@ void NORET_TYPE die(const char *str, struct pt_regs *regs, long err)
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printk("FRAME_POINTER ");
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#endif
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if (current_cpu_data.features & AVR32_FEATURE_OCD) {
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unsigned long did = __mfdr(DBGREG_DID);
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unsigned long did = ocd_read(DID);
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printk("chip: 0x%03lx:0x%04lx rev %lu\n",
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(did >> 1) & 0x7ff,
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(did >> 12) & 0x7fff,
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@ -1,7 +1,7 @@
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/*
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* AVR32 OCD Registers
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* AVR32 OCD Interface and register definitions
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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* Copyright (C) 2004-2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -10,69 +10,529 @@
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#ifndef __ASM_AVR32_OCD_H
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#define __ASM_AVR32_OCD_H
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/* Debug Registers */
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#define DBGREG_DID 0
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#define DBGREG_DC 8
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#define DBGREG_DS 16
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#define DBGREG_RWCS 28
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#define DBGREG_RWA 36
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#define DBGREG_RWD 40
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#define DBGREG_WT 44
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#define DBGREG_DTC 52
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#define DBGREG_DTSA0 56
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#define DBGREG_DTSA1 60
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#define DBGREG_DTEA0 72
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#define DBGREG_DTEA1 76
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#define DBGREG_BWC0A 88
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#define DBGREG_BWC0B 92
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#define DBGREG_BWC1A 96
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#define DBGREG_BWC1B 100
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#define DBGREG_BWC2A 104
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#define DBGREG_BWC2B 108
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#define DBGREG_BWC3A 112
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#define DBGREG_BWC3B 116
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#define DBGREG_BWA0A 120
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#define DBGREG_BWA0B 124
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#define DBGREG_BWA1A 128
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#define DBGREG_BWA1B 132
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#define DBGREG_BWA2A 136
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#define DBGREG_BWA2B 140
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#define DBGREG_BWA3A 144
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#define DBGREG_BWA3B 148
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#define DBGREG_BWD3A 153
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#define DBGREG_BWD3B 156
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/* OCD Register offsets. Abbreviations used below:
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*
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* BP Breakpoint
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* Comm Communication
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* DT Data Trace
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* PC Program Counter
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* PID Process ID
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* R/W Read/Write
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* WP Watchpoint
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*/
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#define OCD_DID 0x0000 /* Device ID */
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#define OCD_DC 0x0008 /* Development Control */
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#define OCD_DS 0x0010 /* Development Status */
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#define OCD_RWCS 0x001c /* R/W Access Control */
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#define OCD_RWA 0x0024 /* R/W Access Address */
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#define OCD_RWD 0x0028 /* R/W Access Data */
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#define OCD_WT 0x002c /* Watchpoint Trigger */
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#define OCD_DTC 0x0034 /* Data Trace Control */
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#define OCD_DTSA0 0x0038 /* DT Start Addr Channel 0 */
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#define OCD_DTSA1 0x003c /* DT Start Addr Channel 1 */
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#define OCD_DTEA0 0x0048 /* DT End Addr Channel 0 */
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#define OCD_DTEA1 0x004c /* DT End Addr Channel 1 */
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#define OCD_BWC0A 0x0058 /* PC BP/WP Control 0A */
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#define OCD_BWC0B 0x005c /* PC BP/WP Control 0B */
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#define OCD_BWC1A 0x0060 /* PC BP/WP Control 1A */
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#define OCD_BWC1B 0x0064 /* PC BP/WP Control 1B */
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#define OCD_BWC2A 0x0068 /* PC BP/WP Control 2A */
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#define OCD_BWC2B 0x006c /* PC BP/WP Control 2B */
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#define OCD_BWC3A 0x0070 /* Data BP/WP Control 3A */
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#define OCD_BWC3B 0x0074 /* Data BP/WP Control 3B */
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#define OCD_BWA0A 0x0078 /* PC BP/WP Address 0A */
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#define OCD_BWA0B 0x007c /* PC BP/WP Address 0B */
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#define OCD_BWA1A 0x0080 /* PC BP/WP Address 1A */
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#define OCD_BWA1B 0x0084 /* PC BP/WP Address 1B */
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#define OCD_BWA2A 0x0088 /* PC BP/WP Address 2A */
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#define OCD_BWA2B 0x008c /* PC BP/WP Address 2B */
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#define OCD_BWA3A 0x0090 /* Data BP/WP Address 3A */
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#define OCD_BWA3B 0x0094 /* Data BP/WP Address 3B */
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#define OCD_NXCFG 0x0100 /* Nexus Configuration */
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#define OCD_DINST 0x0104 /* Debug Instruction */
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#define OCD_DPC 0x0108 /* Debug Program Counter */
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#define OCD_CPUCM 0x010c /* CPU Control Mask */
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#define OCD_DCCPU 0x0110 /* Debug Comm CPU */
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#define OCD_DCEMU 0x0114 /* Debug Comm Emulator */
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#define OCD_DCSR 0x0118 /* Debug Comm Status */
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#define OCD_PID 0x011c /* Ownership Trace PID */
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#define OCD_EPC0 0x0120 /* Event Pair Control 0 */
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#define OCD_EPC1 0x0124 /* Event Pair Control 1 */
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#define OCD_EPC2 0x0128 /* Event Pair Control 2 */
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#define OCD_EPC3 0x012c /* Event Pair Control 3 */
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#define OCD_AXC 0x0130 /* AUX port Control */
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#define DBGREG_PID 284
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/* Bits in DID */
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#define OCD_DID_MID_START 1
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#define OCD_DID_MID_SIZE 11
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#define OCD_DID_PN_START 12
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#define OCD_DID_PN_SIZE 16
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#define OCD_DID_RN_START 28
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#define OCD_DID_RN_SIZE 4
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#define SABAH_OCD 0x01
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#define SABAH_ICACHE 0x02
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#define SABAH_MEM_CACHED 0x04
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#define SABAH_MEM_UNCACHED 0x05
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/* Bits in DC */
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#define OCD_DC_TM_START 0
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#define OCD_DC_TM_SIZE 2
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#define OCD_DC_EIC_START 3
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#define OCD_DC_EIC_SIZE 2
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#define OCD_DC_OVC_START 5
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#define OCD_DC_OVC_SIZE 3
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#define OCD_DC_SS_BIT 8
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#define OCD_DC_DBR_BIT 12
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#define OCD_DC_DBE_BIT 13
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#define OCD_DC_EOS_START 20
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#define OCD_DC_EOS_SIZE 2
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#define OCD_DC_SQA_BIT 22
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#define OCD_DC_IRP_BIT 23
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#define OCD_DC_IFM_BIT 24
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#define OCD_DC_TOZ_BIT 25
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#define OCD_DC_TSR_BIT 26
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#define OCD_DC_RID_BIT 27
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#define OCD_DC_ORP_BIT 28
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#define OCD_DC_MM_BIT 29
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#define OCD_DC_RES_BIT 30
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#define OCD_DC_ABORT_BIT 31
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/* Fields in the Development Control register */
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#define DC_SS_BIT 8
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/* Bits in DS */
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#define OCD_DS_SSS_BIT 0
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#define OCD_DS_SWB_BIT 1
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#define OCD_DS_HWB_BIT 2
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#define OCD_DS_HWE_BIT 3
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#define OCD_DS_STP_BIT 4
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#define OCD_DS_DBS_BIT 5
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#define OCD_DS_BP_START 8
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#define OCD_DS_BP_SIZE 8
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#define OCD_DS_INC_BIT 24
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#define OCD_DS_BOZ_BIT 25
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#define OCD_DS_DBA_BIT 26
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#define OCD_DS_EXB_BIT 27
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#define OCD_DS_NTBF_BIT 28
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#define DC_SS (1 << DC_SS_BIT)
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#define DC_DBE (1 << 13)
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#define DC_RID (1 << 27)
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#define DC_ORP (1 << 28)
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#define DC_MM (1 << 29)
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#define DC_RES (1 << 30)
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/* Bits in RWCS */
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#define OCD_RWCS_DV_BIT 0
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#define OCD_RWCS_ERR_BIT 1
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#define OCD_RWCS_CNT_START 2
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#define OCD_RWCS_CNT_SIZE 14
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#define OCD_RWCS_CRC_BIT 19
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#define OCD_RWCS_NTBC_START 20
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#define OCD_RWCS_NTBC_SIZE 2
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#define OCD_RWCS_NTE_BIT 22
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#define OCD_RWCS_NTAP_BIT 23
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#define OCD_RWCS_WRAPPED_BIT 24
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#define OCD_RWCS_CCTRL_START 25
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#define OCD_RWCS_CCTRL_SIZE 2
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#define OCD_RWCS_SZ_START 27
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#define OCD_RWCS_SZ_SIZE 3
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#define OCD_RWCS_RW_BIT 30
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#define OCD_RWCS_AC_BIT 31
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/* Fields in the Development Status register */
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#define DS_SSS (1 << 0)
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#define DS_SWB (1 << 1)
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#define DS_HWB (1 << 2)
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#define DS_BP_SHIFT 8
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#define DS_BP_MASK (0xff << DS_BP_SHIFT)
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/* Bits in RWA */
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#define OCD_RWA_RWA_START 0
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#define OCD_RWA_RWA_SIZE 32
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#define __mfdr(addr) \
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({ \
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register unsigned long value; \
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asm volatile("mfdr %0, %1" : "=r"(value) : "i"(addr)); \
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value; \
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})
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#define __mtdr(addr, value) \
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asm volatile("mtdr %0, %1" : : "i"(addr), "r"(value))
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/* Bits in RWD */
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#define OCD_RWD_RWD_START 0
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#define OCD_RWD_RWD_SIZE 32
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/* Bits in WT */
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#define OCD_WT_DTE_START 20
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#define OCD_WT_DTE_SIZE 3
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#define OCD_WT_DTS_START 23
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#define OCD_WT_DTS_SIZE 3
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#define OCD_WT_PTE_START 26
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#define OCD_WT_PTE_SIZE 3
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#define OCD_WT_PTS_START 29
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#define OCD_WT_PTS_SIZE 3
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/* Bits in DTC */
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#define OCD_DTC_T0WP_BIT 0
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#define OCD_DTC_T1WP_BIT 1
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#define OCD_DTC_ASID0EN_BIT 2
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#define OCD_DTC_ASID0_START 3
|
||||
#define OCD_DTC_ASID0_SIZE 8
|
||||
#define OCD_DTC_ASID1EN_BIT 11
|
||||
#define OCD_DTC_ASID1_START 12
|
||||
#define OCD_DTC_ASID1_SIZE 8
|
||||
#define OCD_DTC_RWT1_START 28
|
||||
#define OCD_DTC_RWT1_SIZE 2
|
||||
#define OCD_DTC_RWT0_START 30
|
||||
#define OCD_DTC_RWT0_SIZE 2
|
||||
|
||||
/* Bits in DTSA0 */
|
||||
#define OCD_DTSA0_DTSA_START 0
|
||||
#define OCD_DTSA0_DTSA_SIZE 32
|
||||
|
||||
/* Bits in DTSA1 */
|
||||
#define OCD_DTSA1_DTSA_START 0
|
||||
#define OCD_DTSA1_DTSA_SIZE 32
|
||||
|
||||
/* Bits in DTEA0 */
|
||||
#define OCD_DTEA0_DTEA_START 0
|
||||
#define OCD_DTEA0_DTEA_SIZE 32
|
||||
|
||||
/* Bits in DTEA1 */
|
||||
#define OCD_DTEA1_DTEA_START 0
|
||||
#define OCD_DTEA1_DTEA_SIZE 32
|
||||
|
||||
/* Bits in BWC0A */
|
||||
#define OCD_BWC0A_ASIDEN_BIT 0
|
||||
#define OCD_BWC0A_ASID_START 1
|
||||
#define OCD_BWC0A_ASID_SIZE 8
|
||||
#define OCD_BWC0A_EOC_BIT 14
|
||||
#define OCD_BWC0A_AME_BIT 25
|
||||
#define OCD_BWC0A_BWE_START 30
|
||||
#define OCD_BWC0A_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWC0B */
|
||||
#define OCD_BWC0B_ASIDEN_BIT 0
|
||||
#define OCD_BWC0B_ASID_START 1
|
||||
#define OCD_BWC0B_ASID_SIZE 8
|
||||
#define OCD_BWC0B_EOC_BIT 14
|
||||
#define OCD_BWC0B_AME_BIT 25
|
||||
#define OCD_BWC0B_BWE_START 30
|
||||
#define OCD_BWC0B_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWC1A */
|
||||
#define OCD_BWC1A_ASIDEN_BIT 0
|
||||
#define OCD_BWC1A_ASID_START 1
|
||||
#define OCD_BWC1A_ASID_SIZE 8
|
||||
#define OCD_BWC1A_EOC_BIT 14
|
||||
#define OCD_BWC1A_AME_BIT 25
|
||||
#define OCD_BWC1A_BWE_START 30
|
||||
#define OCD_BWC1A_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWC1B */
|
||||
#define OCD_BWC1B_ASIDEN_BIT 0
|
||||
#define OCD_BWC1B_ASID_START 1
|
||||
#define OCD_BWC1B_ASID_SIZE 8
|
||||
#define OCD_BWC1B_EOC_BIT 14
|
||||
#define OCD_BWC1B_AME_BIT 25
|
||||
#define OCD_BWC1B_BWE_START 30
|
||||
#define OCD_BWC1B_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWC2A */
|
||||
#define OCD_BWC2A_ASIDEN_BIT 0
|
||||
#define OCD_BWC2A_ASID_START 1
|
||||
#define OCD_BWC2A_ASID_SIZE 8
|
||||
#define OCD_BWC2A_EOC_BIT 14
|
||||
#define OCD_BWC2A_AMB_START 20
|
||||
#define OCD_BWC2A_AMB_SIZE 5
|
||||
#define OCD_BWC2A_AME_BIT 25
|
||||
#define OCD_BWC2A_BWE_START 30
|
||||
#define OCD_BWC2A_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWC2B */
|
||||
#define OCD_BWC2B_ASIDEN_BIT 0
|
||||
#define OCD_BWC2B_ASID_START 1
|
||||
#define OCD_BWC2B_ASID_SIZE 8
|
||||
#define OCD_BWC2B_EOC_BIT 14
|
||||
#define OCD_BWC2B_AME_BIT 25
|
||||
#define OCD_BWC2B_BWE_START 30
|
||||
#define OCD_BWC2B_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWC3A */
|
||||
#define OCD_BWC3A_ASIDEN_BIT 0
|
||||
#define OCD_BWC3A_ASID_START 1
|
||||
#define OCD_BWC3A_ASID_SIZE 8
|
||||
#define OCD_BWC3A_SIZE_START 9
|
||||
#define OCD_BWC3A_SIZE_SIZE 3
|
||||
#define OCD_BWC3A_EOC_BIT 14
|
||||
#define OCD_BWC3A_BWO_START 16
|
||||
#define OCD_BWC3A_BWO_SIZE 2
|
||||
#define OCD_BWC3A_BME_START 20
|
||||
#define OCD_BWC3A_BME_SIZE 4
|
||||
#define OCD_BWC3A_BRW_START 28
|
||||
#define OCD_BWC3A_BRW_SIZE 2
|
||||
#define OCD_BWC3A_BWE_START 30
|
||||
#define OCD_BWC3A_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWC3B */
|
||||
#define OCD_BWC3B_ASIDEN_BIT 0
|
||||
#define OCD_BWC3B_ASID_START 1
|
||||
#define OCD_BWC3B_ASID_SIZE 8
|
||||
#define OCD_BWC3B_SIZE_START 9
|
||||
#define OCD_BWC3B_SIZE_SIZE 3
|
||||
#define OCD_BWC3B_EOC_BIT 14
|
||||
#define OCD_BWC3B_BWO_START 16
|
||||
#define OCD_BWC3B_BWO_SIZE 2
|
||||
#define OCD_BWC3B_BME_START 20
|
||||
#define OCD_BWC3B_BME_SIZE 4
|
||||
#define OCD_BWC3B_BRW_START 28
|
||||
#define OCD_BWC3B_BRW_SIZE 2
|
||||
#define OCD_BWC3B_BWE_START 30
|
||||
#define OCD_BWC3B_BWE_SIZE 2
|
||||
|
||||
/* Bits in BWA0A */
|
||||
#define OCD_BWA0A_BWA_START 0
|
||||
#define OCD_BWA0A_BWA_SIZE 32
|
||||
|
||||
/* Bits in BWA0B */
|
||||
#define OCD_BWA0B_BWA_START 0
|
||||
#define OCD_BWA0B_BWA_SIZE 32
|
||||
|
||||
/* Bits in BWA1A */
|
||||
#define OCD_BWA1A_BWA_START 0
|
||||
#define OCD_BWA1A_BWA_SIZE 32
|
||||
|
||||
/* Bits in BWA1B */
|
||||
#define OCD_BWA1B_BWA_START 0
|
||||
#define OCD_BWA1B_BWA_SIZE 32
|
||||
|
||||
/* Bits in BWA2A */
|
||||
#define OCD_BWA2A_BWA_START 0
|
||||
#define OCD_BWA2A_BWA_SIZE 32
|
||||
|
||||
/* Bits in BWA2B */
|
||||
#define OCD_BWA2B_BWA_START 0
|
||||
#define OCD_BWA2B_BWA_SIZE 32
|
||||
|
||||
/* Bits in BWA3A */
|
||||
#define OCD_BWA3A_BWA_START 0
|
||||
#define OCD_BWA3A_BWA_SIZE 32
|
||||
|
||||
/* Bits in BWA3B */
|
||||
#define OCD_BWA3B_BWA_START 0
|
||||
#define OCD_BWA3B_BWA_SIZE 32
|
||||
|
||||
/* Bits in NXCFG */
|
||||
#define OCD_NXCFG_NXARCH_START 0
|
||||
#define OCD_NXCFG_NXARCH_SIZE 4
|
||||
#define OCD_NXCFG_NXOCD_START 4
|
||||
#define OCD_NXCFG_NXOCD_SIZE 4
|
||||
#define OCD_NXCFG_NXPCB_START 8
|
||||
#define OCD_NXCFG_NXPCB_SIZE 4
|
||||
#define OCD_NXCFG_NXDB_START 12
|
||||
#define OCD_NXCFG_NXDB_SIZE 4
|
||||
#define OCD_NXCFG_MXMSEO_BIT 16
|
||||
#define OCD_NXCFG_NXMDO_START 17
|
||||
#define OCD_NXCFG_NXMDO_SIZE 4
|
||||
#define OCD_NXCFG_NXPT_BIT 21
|
||||
#define OCD_NXCFG_NXOT_BIT 22
|
||||
#define OCD_NXCFG_NXDWT_BIT 23
|
||||
#define OCD_NXCFG_NXDRT_BIT 24
|
||||
#define OCD_NXCFG_NXDTC_START 25
|
||||
#define OCD_NXCFG_NXDTC_SIZE 3
|
||||
#define OCD_NXCFG_NXDMA_BIT 28
|
||||
|
||||
/* Bits in DINST */
|
||||
#define OCD_DINST_DINST_START 0
|
||||
#define OCD_DINST_DINST_SIZE 32
|
||||
|
||||
/* Bits in CPUCM */
|
||||
#define OCD_CPUCM_BEM_BIT 1
|
||||
#define OCD_CPUCM_FEM_BIT 2
|
||||
#define OCD_CPUCM_REM_BIT 3
|
||||
#define OCD_CPUCM_IBEM_BIT 4
|
||||
#define OCD_CPUCM_IEEM_BIT 5
|
||||
|
||||
/* Bits in DCCPU */
|
||||
#define OCD_DCCPU_DATA_START 0
|
||||
#define OCD_DCCPU_DATA_SIZE 32
|
||||
|
||||
/* Bits in DCEMU */
|
||||
#define OCD_DCEMU_DATA_START 0
|
||||
#define OCD_DCEMU_DATA_SIZE 32
|
||||
|
||||
/* Bits in DCSR */
|
||||
#define OCD_DCSR_CPUD_BIT 0
|
||||
#define OCD_DCSR_EMUD_BIT 1
|
||||
|
||||
/* Bits in PID */
|
||||
#define OCD_PID_PROCESS_START 0
|
||||
#define OCD_PID_PROCESS_SIZE 32
|
||||
|
||||
/* Bits in EPC0 */
|
||||
#define OCD_EPC0_RNG_START 0
|
||||
#define OCD_EPC0_RNG_SIZE 2
|
||||
#define OCD_EPC0_CE_BIT 4
|
||||
#define OCD_EPC0_ECNT_START 16
|
||||
#define OCD_EPC0_ECNT_SIZE 16
|
||||
|
||||
/* Bits in EPC1 */
|
||||
#define OCD_EPC1_RNG_START 0
|
||||
#define OCD_EPC1_RNG_SIZE 2
|
||||
#define OCD_EPC1_ATB_BIT 5
|
||||
#define OCD_EPC1_AM_BIT 6
|
||||
|
||||
/* Bits in EPC2 */
|
||||
#define OCD_EPC2_RNG_START 0
|
||||
#define OCD_EPC2_RNG_SIZE 2
|
||||
#define OCD_EPC2_DB_START 2
|
||||
#define OCD_EPC2_DB_SIZE 2
|
||||
|
||||
/* Bits in EPC3 */
|
||||
#define OCD_EPC3_RNG_START 0
|
||||
#define OCD_EPC3_RNG_SIZE 2
|
||||
#define OCD_EPC3_DWE_BIT 2
|
||||
|
||||
/* Bits in AXC */
|
||||
#define OCD_AXC_DIV_START 0
|
||||
#define OCD_AXC_DIV_SIZE 4
|
||||
#define OCD_AXC_AXE_BIT 8
|
||||
#define OCD_AXC_AXS_BIT 9
|
||||
#define OCD_AXC_DDR_BIT 10
|
||||
#define OCD_AXC_LS_BIT 11
|
||||
#define OCD_AXC_REX_BIT 12
|
||||
#define OCD_AXC_REXTEN_BIT 13
|
||||
|
||||
/* Constants for DC:EIC */
|
||||
#define OCD_EIC_PROGRAM_AND_DATA_TRACE 0
|
||||
#define OCD_EIC_BREAKPOINT 1
|
||||
#define OCD_EIC_NOP 2
|
||||
|
||||
/* Constants for DC:OVC */
|
||||
#define OCD_OVC_OVERRUN 0
|
||||
#define OCD_OVC_DELAY_CPU_BTM 1
|
||||
#define OCD_OVC_DELAY_CPU_DTM 2
|
||||
#define OCD_OVC_DELAY_CPU_BTM_DTM 3
|
||||
|
||||
/* Constants for DC:EOS */
|
||||
#define OCD_EOS_NOP 0
|
||||
#define OCD_EOS_DEBUG_MODE 1
|
||||
#define OCD_EOS_BREAKPOINT_WATCHPOINT 2
|
||||
#define OCD_EOS_THQ 3
|
||||
|
||||
/* Constants for RWCS:NTBC */
|
||||
#define OCD_NTBC_OVERWRITE 0
|
||||
#define OCD_NTBC_DISABLE 1
|
||||
#define OCD_NTBC_BREAKPOINT 2
|
||||
|
||||
/* Constants for RWCS:CCTRL */
|
||||
#define OCD_CCTRL_AUTO 0
|
||||
#define OCD_CCTRL_CACHED 1
|
||||
#define OCD_CCTRL_UNCACHED 2
|
||||
|
||||
/* Constants for RWCS:SZ */
|
||||
#define OCD_SZ_BYTE 0
|
||||
#define OCD_SZ_HALFWORD 1
|
||||
#define OCD_SZ_WORD 2
|
||||
|
||||
/* Constants for WT:PTS */
|
||||
#define OCD_PTS_DISABLED 0
|
||||
#define OCD_PTS_PROGRAM_0B 1
|
||||
#define OCD_PTS_PROGRAM_1A 2
|
||||
#define OCD_PTS_PROGRAM_1B 3
|
||||
#define OCD_PTS_PROGRAM_2A 4
|
||||
#define OCD_PTS_PROGRAM_2B 5
|
||||
#define OCD_PTS_DATA_3A 6
|
||||
#define OCD_PTS_DATA_3B 7
|
||||
|
||||
/* Constants for DTC:RWT1 */
|
||||
#define OCD_RWT1_NO_TRACE 0
|
||||
#define OCD_RWT1_DATA_READ 1
|
||||
#define OCD_RWT1_DATA_WRITE 2
|
||||
#define OCD_RWT1_DATA_READ_WRITE 3
|
||||
|
||||
/* Constants for DTC:RWT0 */
|
||||
#define OCD_RWT0_NO_TRACE 0
|
||||
#define OCD_RWT0_DATA_READ 1
|
||||
#define OCD_RWT0_DATA_WRITE 2
|
||||
#define OCD_RWT0_DATA_READ_WRITE 3
|
||||
|
||||
/* Constants for BWC0A:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for BWC0B:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for BWC1A:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for BWC1B:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for BWC2A:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for BWC2B:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for BWC3A:SIZE */
|
||||
#define OCD_SIZE_BYTE_ACCESS 4
|
||||
#define OCD_SIZE_HALFWORD_ACCESS 5
|
||||
#define OCD_SIZE_WORD_ACCESS 6
|
||||
#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
|
||||
|
||||
/* Constants for BWC3A:BRW */
|
||||
#define OCD_BRW_READ_BREAK 0
|
||||
#define OCD_BRW_WRITE_BREAK 1
|
||||
#define OCD_BRW_ANY_ACCES_BREAK 2
|
||||
|
||||
/* Constants for BWC3A:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for BWC3B:SIZE */
|
||||
#define OCD_SIZE_BYTE_ACCESS 4
|
||||
#define OCD_SIZE_HALFWORD_ACCESS 5
|
||||
#define OCD_SIZE_WORD_ACCESS 6
|
||||
#define OCD_SIZE_DOUBLE_WORD_ACCESS 7
|
||||
|
||||
/* Constants for BWC3B:BRW */
|
||||
#define OCD_BRW_READ_BREAK 0
|
||||
#define OCD_BRW_WRITE_BREAK 1
|
||||
#define OCD_BRW_ANY_ACCES_BREAK 2
|
||||
|
||||
/* Constants for BWC3B:BWE */
|
||||
#define OCD_BWE_DISABLED 0
|
||||
#define OCD_BWE_BREAKPOINT_ENABLED 1
|
||||
#define OCD_BWE_WATCHPOINT_ENABLED 3
|
||||
|
||||
/* Constants for EPC0:RNG */
|
||||
#define OCD_RNG_DISABLED 0
|
||||
#define OCD_RNG_EXCLUSIVE 1
|
||||
#define OCD_RNG_INCLUSIVE 2
|
||||
|
||||
/* Constants for EPC1:RNG */
|
||||
#define OCD_RNG_DISABLED 0
|
||||
#define OCD_RNG_EXCLUSIVE 1
|
||||
#define OCD_RNG_INCLUSIVE 2
|
||||
|
||||
/* Constants for EPC2:RNG */
|
||||
#define OCD_RNG_DISABLED 0
|
||||
#define OCD_RNG_EXCLUSIVE 1
|
||||
#define OCD_RNG_INCLUSIVE 2
|
||||
|
||||
/* Constants for EPC2:DB */
|
||||
#define OCD_DB_DISABLED 0
|
||||
#define OCD_DB_CHAINED_B 1
|
||||
#define OCD_DB_CHAINED_A 2
|
||||
#define OCD_DB_AHAINED_A_AND_B 3
|
||||
|
||||
/* Constants for EPC3:RNG */
|
||||
#define OCD_RNG_DISABLED 0
|
||||
#define OCD_RNG_EXCLUSIVE 1
|
||||
#define OCD_RNG_INCLUSIVE 2
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/* Register access macros */
|
||||
static inline unsigned long __ocd_read(unsigned int reg)
|
||||
{
|
||||
return __builtin_mfdr(reg);
|
||||
}
|
||||
|
||||
static inline void __ocd_write(unsigned int reg, unsigned long value)
|
||||
{
|
||||
__builtin_mtdr(reg, value);
|
||||
}
|
||||
|
||||
#define ocd_read(reg) __ocd_read(OCD_##reg)
|
||||
#define ocd_write(reg, value) __ocd_write(OCD_##reg, value)
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
#endif /* __ASM_AVR32_OCD_H */
|
||||
|
||||
@ -35,8 +35,8 @@
|
||||
#include <asm/ocd.h>
|
||||
#define finish_arch_switch(prev) \
|
||||
do { \
|
||||
__mtdr(DBGREG_PID, prev->pid); \
|
||||
__mtdr(DBGREG_PID, current->pid); \
|
||||
ocd_write(PID, prev->pid); \
|
||||
ocd_write(PID, current->pid); \
|
||||
} while(0)
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user