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Merge branch 'devicetree/merge' into devicetree/next

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This commit is contained in:
Grant Likely 2012-05-20 20:18:37 -06:00
commit 8d6c1efa51
2 changed files with 43 additions and 4 deletions
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35
Documentation/devicetree/bindings/arm/gic.txt
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@ -11,7 +11,9 @@ have PPIs or SGIs.
Main node required properties: Main node required properties:
- compatible : should be one of: - compatible : should be one of:
"arm,cortex-a15-gic"
"arm,cortex-a9-gic" "arm,cortex-a9-gic"
"arm,cortex-a7-gic"
"arm,arm11mp-gic" "arm,arm11mp-gic"
- interrupt-controller : Identifies the node as an interrupt controller - interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an - #interrupt-cells : Specifies the number of cells needed to encode an
@ -39,8 +41,9 @@ Main node required properties:
the GIC cpu interface register base and size. the GIC cpu interface register base and size.
Optional Optional
- interrupts : Interrupt source of the parent interrupt controller. Only - interrupts : Interrupt source of the parent interrupt controller on
present on secondary GICs. secondary GICs, or VGIC maintainance interrupt on primary GIC (see
below).
- cpu-offset : per-cpu offset within the distributor and cpu interface - cpu-offset : per-cpu offset within the distributor and cpu interface
regions, used when the GIC doesn't have banked registers. The offset is regions, used when the GIC doesn't have banked registers. The offset is
@ -57,3 +60,31 @@ Example:
<0xfff10100 0x100>; <0xfff10100 0x100>;
}; };
* GIC virtualization extensions (VGIC)
For ARM cores that support the virtualization extensions, additional
properties must be described (they only exist if the GIC is the
primary interrupt controller).
Required properties:
- reg : Additional regions specifying the base physical address and
size of the VGIC registers. The first additional region is the GIC
virtual interface control register base and size. The 2nd additional
region is the GIC virtual cpu interface register base and size.
- interrupts : VGIC maintainance interrupt.
Example:
interrupt-controller@2c001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2c001000 0x1000>,
<0x2c002000 0x1000>,
<0x2c004000 0x2000>,
<0x2c006000 0x2000>;
interrupts = <1 9 0xf04>;
};

12
include/linux/of_irq.h
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@ -11,7 +11,7 @@ struct of_irq;
#include <linux/of.h> #include <linux/of.h>
/* /*
* irq_of_parse_and_map() is used ba all OF enabled platforms; but SPARC * irq_of_parse_and_map() is used by all OF enabled platforms; but SPARC
* implements it differently. However, the prototype is the same for all, * implements it differently. However, the prototype is the same for all,
* so declare it here regardless of the CONFIG_OF_IRQ setting. * so declare it here regardless of the CONFIG_OF_IRQ setting.
*/ */
@ -76,5 +76,13 @@ extern struct device_node *of_irq_find_parent(struct device_node *child);
extern void of_irq_init(const struct of_device_id *matches); extern void of_irq_init(const struct of_device_id *matches);
#endif /* CONFIG_OF_IRQ */ #endif /* CONFIG_OF_IRQ */
#endif /* CONFIG_OF */
#else /* !CONFIG_OF */
static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
int index)
{
return 0;
}
#endif /* !CONFIG_OF */
#endif /* __OF_IRQ_H */ #endif /* __OF_IRQ_H */