renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-30 08:04:13 +08:00
Code

MIPS: kernel: r4k_fpu: Add support for MIPS R6

Browse Source 
Add the MIPS R6 related preprocessor definitions for FPU signal
related functions. MIPS R6 only has FR=1 so avoid checking that
bit on the C0/Status register.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Leonid Yegoshin 2014-11-25 10:08:45 +00:00 committed by Markos Chandras
parent 207083b1da
commit 8d5b9b771e
1 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/mips/kernel/r4k_fpu.S
View File

@ -34,7 +34,7 @@
.endm
.set noreorder
.set arch=r4000
.set MIPS_ISA_ARCH_LEVEL_RAW
LEAF(_save_fp_context)
.set push
@ -42,7 +42,8 @@ LEAF(_save_fp_context)
cfc1 t1, fcr31
.set pop
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
defined(CONFIG_CPU_MIPS32_R6)
.set push
SET_HARDFLOAT
#ifdef CONFIG_CPU_MIPS32_R2
@ -105,10 +106,12 @@ LEAF(_save_fp_context32)
SET_HARDFLOAT
cfc1 t1, fcr31
#ifndef CONFIG_CPU_MIPS64_R6
mfc0 t0, CP0_STATUS
sll t0, t0, 5
bgez t0, 1f # skip storing odd if FR=0
nop
#endif
/* Store the 16 odd double precision registers */
EX sdc1 $f1, SC32_FPREGS+8(a0)
@ -163,7 +166,8 @@ LEAF(_save_fp_context32)
LEAF(_restore_fp_context)
EX lw t1, SC_FPC_CSR(a0)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
defined(CONFIG_CPU_MIPS32_R6)
.set push
SET_HARDFLOAT
#ifdef CONFIG_CPU_MIPS32_R2
@ -223,10 +227,12 @@ LEAF(_restore_fp_context32)
SET_HARDFLOAT
EX lw t1, SC32_FPC_CSR(a0)
#ifndef CONFIG_CPU_MIPS64_R6
mfc0 t0, CP0_STATUS
sll t0, t0, 5
bgez t0, 1f # skip loading odd if FR=0
nop
#endif
EX ldc1 $f1, SC32_FPREGS+8(a0)
EX ldc1 $f3, SC32_FPREGS+24(a0)