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mmc: sdhci_omap: Add support to set IODELAY values
The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to set the IODELAY values depending on the various MMC modes using the pinctrl APIs. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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7d33c35815
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@ -25,6 +25,7 @@
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pinctrl/consumer.h>
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#include "sdhci-pltfm.h"
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@ -90,8 +91,12 @@
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#define MAX_PHASE_DELAY 0x7C
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/* sdhci-omap controller flags */
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#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
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struct sdhci_omap_data {
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u32 offset;
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u8 flags;
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};
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struct sdhci_omap_host {
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@ -102,8 +107,16 @@ struct sdhci_omap_host {
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struct sdhci_host *host;
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u8 bus_mode;
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u8 power_mode;
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u8 timing;
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u8 flags;
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struct pinctrl *pinctrl;
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struct pinctrl_state **pinctrl_state;
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};
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static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
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static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
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static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
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unsigned int offset)
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{
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@ -436,6 +449,31 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
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return 0;
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}
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static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
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{
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int ret;
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struct pinctrl_state *pinctrl_state;
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struct device *dev = omap_host->dev;
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if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
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return;
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if (omap_host->timing == timing)
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return;
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sdhci_omap_stop_clock(omap_host);
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pinctrl_state = omap_host->pinctrl_state[timing];
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ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
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if (ret) {
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dev_err(dev, "failed to select pinctrl state\n");
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return;
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}
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sdhci_omap_start_clock(omap_host);
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omap_host->timing = timing;
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}
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static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
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u8 power_mode)
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{
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@ -472,6 +510,7 @@ static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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omap_host = sdhci_pltfm_priv(pltfm_host);
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sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
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sdhci_omap_set_timing(omap_host, ios->timing);
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sdhci_set_ios(mmc, ios);
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sdhci_omap_set_power_mode(omap_host, ios->power_mode);
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}
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@ -680,6 +719,7 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
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static const struct sdhci_omap_data dra7_data = {
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.offset = 0x200,
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.flags = SDHCI_OMAP_REQUIRE_IODELAY,
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};
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static const struct of_device_id omap_sdhci_match[] = {
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@ -688,6 +728,108 @@ static const struct of_device_id omap_sdhci_match[] = {
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};
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MODULE_DEVICE_TABLE(of, omap_sdhci_match);
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static struct pinctrl_state
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*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
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u32 *caps, u32 capmask)
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{
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struct device *dev = omap_host->dev;
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struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
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if (!(*caps & capmask))
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goto ret;
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pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
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if (IS_ERR(pinctrl_state)) {
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dev_err(dev, "no pinctrl state for %s mode", mode);
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*caps &= ~capmask;
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}
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ret:
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return pinctrl_state;
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}
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static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
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*omap_host)
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{
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struct device *dev = omap_host->dev;
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struct sdhci_host *host = omap_host->host;
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struct mmc_host *mmc = host->mmc;
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u32 *caps = &mmc->caps;
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u32 *caps2 = &mmc->caps2;
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struct pinctrl_state *state;
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struct pinctrl_state **pinctrl_state;
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if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
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return 0;
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pinctrl_state = devm_kzalloc(dev, sizeof(*pinctrl_state) *
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(MMC_TIMING_MMC_HS200 + 1), GFP_KERNEL);
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if (!pinctrl_state)
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return -ENOMEM;
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omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
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if (IS_ERR(omap_host->pinctrl)) {
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dev_err(dev, "Cannot get pinctrl\n");
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return PTR_ERR(omap_host->pinctrl);
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}
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state = pinctrl_lookup_state(omap_host->pinctrl, "default");
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if (IS_ERR(state)) {
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dev_err(dev, "no pinctrl state for default mode\n");
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return PTR_ERR(state);
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}
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pinctrl_state[MMC_TIMING_LEGACY] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
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MMC_CAP_UHS_SDR104);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
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MMC_CAP_UHS_DDR50);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
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MMC_CAP_UHS_SDR50);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
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MMC_CAP_UHS_SDR25);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
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MMC_CAP_UHS_SDR12);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
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MMC_CAP_1_8V_DDR);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
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MMC_CAP_SD_HIGHSPEED);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_SD_HS] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
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MMC_CAP_MMC_HIGHSPEED);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_MMC_HS] = state;
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state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
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MMC_CAP2_HS200_1_8V_SDR);
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if (!IS_ERR(state))
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pinctrl_state[MMC_TIMING_MMC_HS200] = state;
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omap_host->pinctrl_state = pinctrl_state;
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return 0;
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}
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static int sdhci_omap_probe(struct platform_device *pdev)
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{
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int ret;
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@ -724,6 +866,8 @@ static int sdhci_omap_probe(struct platform_device *pdev)
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omap_host->base = host->ioaddr;
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omap_host->dev = dev;
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omap_host->power_mode = MMC_POWER_UNDEFINED;
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omap_host->timing = MMC_TIMING_LEGACY;
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omap_host->flags = data->flags;
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host->ioaddr += offset;
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mmc = host->mmc;
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@ -772,6 +916,10 @@ static int sdhci_omap_probe(struct platform_device *pdev)
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goto err_put_sync;
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}
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ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
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if (ret)
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goto err_put_sync;
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host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
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host->mmc_host_ops.start_signal_voltage_switch =
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sdhci_omap_start_signal_voltage_switch;
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