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drm/amdgpu: add context buffer size check for HEVC
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -374,7 +374,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
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unsigned height_in_mb = ALIGN(height / 16, 2);
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unsigned fs_in_mb = width_in_mb * height_in_mb;
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unsigned image_size, tmp, min_dpb_size, num_dpb_buffer;
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unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size;
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image_size = width * height;
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image_size += image_size / 2;
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@ -466,6 +466,8 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
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num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2;
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min_dpb_size = image_size * num_dpb_buffer;
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min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16)
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* 16 * num_dpb_buffer + 52 * 1024;
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break;
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default:
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@ -486,6 +488,7 @@ static int amdgpu_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
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buf_sizes[0x1] = dpb_size;
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buf_sizes[0x2] = image_size;
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buf_sizes[0x4] = min_ctx_size;
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return 0;
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}
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@ -628,6 +631,13 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
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return -EINVAL;
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}
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} else if (cmd == 0x206) {
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if ((end - start) < ctx->buf_sizes[4]) {
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DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
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(unsigned)(end - start),
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ctx->buf_sizes[4]);
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return -EINVAL;
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}
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} else if ((cmd != 0x100) && (cmd != 0x204)) {
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DRM_ERROR("invalid UVD command %X!\n", cmd);
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return -EINVAL;
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@ -755,9 +765,10 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
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struct amdgpu_uvd_cs_ctx ctx = {};
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unsigned buf_sizes[] = {
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[0x00000000] = 2048,
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[0x00000001] = 32 * 1024 * 1024,
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[0x00000002] = 2048 * 1152 * 3,
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[0x00000001] = 0xFFFFFFFF,
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[0x00000002] = 0xFFFFFFFF,
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[0x00000003] = 2048,
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[0x00000004] = 0xFFFFFFFF,
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};
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struct amdgpu_ib *ib = &parser->ibs[ib_idx];
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int r;
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