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drm/tegra: dpaux: Registers are 32-bit
Use a sized unsigned 32-bit data type (u32) to store register contents. The DPAUX registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -56,15 +56,14 @@ static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
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return container_of(work, struct tegra_dpaux, work);
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}
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static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
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unsigned long offset)
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static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
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unsigned long offset)
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{
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return readl(dpaux->regs + (offset << 2));
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}
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static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
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unsigned long value,
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unsigned long offset)
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u32 value, unsigned long offset)
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{
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writel(value, dpaux->regs + (offset << 2));
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}
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@ -76,7 +75,7 @@ static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
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for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
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size_t num = min_t(size_t, size - i * 4, 4);
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unsigned long value = 0;
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u32 value = 0;
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for (j = 0; j < num; j++)
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value |= buffer[i * 4 + j] << (j * 8);
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@ -92,7 +91,7 @@ static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
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for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
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size_t num = min_t(size_t, size - i * 4, 4);
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unsigned long value;
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u32 value;
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
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@ -248,7 +247,7 @@ static irqreturn_t tegra_dpaux_irq(int irq, void *data)
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{
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struct tegra_dpaux *dpaux = data;
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irqreturn_t ret = IRQ_HANDLED;
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unsigned long value;
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u32 value;
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/* clear interrupts */
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value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
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@ -271,7 +270,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
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{
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struct tegra_dpaux *dpaux;
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struct resource *regs;
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unsigned long value;
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u32 value;
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int err;
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dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
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@ -463,7 +462,7 @@ int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
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enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
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{
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unsigned long value;
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u32 value;
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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@ -475,7 +474,7 @@ enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
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int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
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{
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unsigned long value;
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u32 value;
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value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
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DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
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@ -493,7 +492,7 @@ int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
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int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
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{
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unsigned long value;
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u32 value;
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value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
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value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
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