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https://github.com/edk2-porting/linux-next.git
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Merge branch 'topic/stm32-dma' into for-linus
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commit
8a3ec58382
@ -40,8 +40,7 @@ Example:
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DMA clients connected to the STM32 DMA controller must use the format
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described in the dma.txt file, using a five-cell specifier for each
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channel: a phandle plus four integer cells.
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The four cells in order are:
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channel: a phandle to the DMA controller plus the following four integer cells:
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1. The channel id
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2. The request line number
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@ -61,7 +60,7 @@ The four cells in order are:
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0x1: medium
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0x2: high
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0x3: very high
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5. A 32bit mask specifying the DMA FIFO threshold configuration which are device
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4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
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dependent:
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-bit 0-1: Fifo threshold
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0x0: 1/4 full FIFO
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@ -458,7 +458,7 @@ config STM32_DMA
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help
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Enable support for the on-chip DMA controller on STMicroelectronics
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STM32 MCUs.
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If you have a board based on such a MCU and wish to use DMA say Y or M
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If you have a board based on such a MCU and wish to use DMA say Y
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here.
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config S3C24XX_DMAC
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@ -114,6 +114,7 @@
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#define STM32_DMA_MAX_CHANNELS 0x08
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#define STM32_DMA_MAX_REQUEST_ID 0x08
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#define STM32_DMA_MAX_DATA_PARAM 0x03
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#define STM32_DMA_MAX_BURST 16
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enum stm32_dma_width {
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STM32_DMA_BYTE,
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@ -403,6 +404,13 @@ static int stm32_dma_terminate_all(struct dma_chan *c)
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return 0;
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}
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static void stm32_dma_synchronize(struct dma_chan *c)
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{
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struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
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vchan_synchronize(&chan->vchan);
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}
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static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
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{
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struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
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@ -421,7 +429,7 @@ static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
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dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr);
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}
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static int stm32_dma_start_transfer(struct stm32_dma_chan *chan)
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static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
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{
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struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
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struct virt_dma_desc *vdesc;
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@ -432,12 +440,12 @@ static int stm32_dma_start_transfer(struct stm32_dma_chan *chan)
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ret = stm32_dma_disable_chan(chan);
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if (ret < 0)
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return ret;
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return;
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if (!chan->desc) {
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vdesc = vchan_next_desc(&chan->vchan);
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if (!vdesc)
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return -EPERM;
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return;
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chan->desc = to_stm32_dma_desc(vdesc);
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chan->next_sg = 0;
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@ -471,7 +479,7 @@ static int stm32_dma_start_transfer(struct stm32_dma_chan *chan)
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chan->busy = true;
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return 0;
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dev_dbg(chan2dev(chan), "vchan %p: started\n", &chan->vchan);
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}
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static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
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@ -500,8 +508,6 @@ static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
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dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
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stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
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}
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chan->next_sg++;
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}
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}
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@ -510,6 +516,7 @@ static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan)
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if (chan->desc) {
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if (chan->desc->cyclic) {
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vchan_cyclic_callback(&chan->desc->vdesc);
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chan->next_sg++;
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stm32_dma_configure_next_sg(chan);
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} else {
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chan->busy = false;
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@ -552,15 +559,13 @@ static void stm32_dma_issue_pending(struct dma_chan *c)
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{
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struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&chan->vchan.lock, flags);
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if (!chan->busy) {
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if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
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ret = stm32_dma_start_transfer(chan);
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if ((!ret) && (chan->desc->cyclic))
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stm32_dma_configure_next_sg(chan);
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}
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if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
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dev_dbg(chan2dev(chan), "vchan %p: issued\n", &chan->vchan);
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stm32_dma_start_transfer(chan);
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if (chan->desc->cyclic)
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stm32_dma_configure_next_sg(chan);
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}
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spin_unlock_irqrestore(&chan->vchan.lock, flags);
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}
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@ -848,26 +853,40 @@ static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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}
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static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
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{
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u32 dma_scr, width, ndtr;
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struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
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dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
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width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
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ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
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return ndtr << width;
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}
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static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
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struct stm32_dma_desc *desc,
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u32 next_sg)
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{
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struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
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u32 dma_scr, width, residue, count;
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u32 residue = 0;
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int i;
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residue = 0;
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/*
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* In cyclic mode, for the last period, residue = remaining bytes from
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* NDTR
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*/
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if (chan->desc->cyclic && next_sg == 0)
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return stm32_dma_get_remaining_bytes(chan);
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/*
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* For all other periods in cyclic mode, and in sg mode,
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* residue = remaining bytes from NDTR + remaining periods/sg to be
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* transferred
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*/
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for (i = next_sg; i < desc->num_sgs; i++)
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residue += desc->sg_req[i].len;
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if (next_sg != 0) {
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dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
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width = STM32_DMA_SCR_PSIZE_GET(dma_scr);
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count = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
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residue += count << width;
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}
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residue += stm32_dma_get_remaining_bytes(chan);
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return residue;
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}
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@ -968,30 +987,36 @@ static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct stm32_dma_device *dmadev = ofdma->of_dma_data;
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struct device *dev = dmadev->ddev.dev;
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struct stm32_dma_cfg cfg;
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struct stm32_dma_chan *chan;
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struct dma_chan *c;
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if (dma_spec->args_count < 3)
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if (dma_spec->args_count < 4) {
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dev_err(dev, "Bad number of cells\n");
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return NULL;
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}
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cfg.channel_id = dma_spec->args[0];
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cfg.request_line = dma_spec->args[1];
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cfg.stream_config = dma_spec->args[2];
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cfg.threshold = 0;
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cfg.threshold = dma_spec->args[3];
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if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) || (cfg.request_line >=
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STM32_DMA_MAX_REQUEST_ID))
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if ((cfg.channel_id >= STM32_DMA_MAX_CHANNELS) ||
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(cfg.request_line >= STM32_DMA_MAX_REQUEST_ID)) {
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dev_err(dev, "Bad channel and/or request id\n");
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return NULL;
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if (dma_spec->args_count > 3)
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cfg.threshold = dma_spec->args[3];
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}
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chan = &dmadev->chan[cfg.channel_id];
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c = dma_get_slave_channel(&chan->vchan.chan);
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if (c)
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stm32_dma_set_config(chan, &cfg);
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if (!c) {
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dev_err(dev, "No more channel avalaible\n");
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return NULL;
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}
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stm32_dma_set_config(chan, &cfg);
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return c;
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}
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@ -1055,6 +1080,7 @@ static int stm32_dma_probe(struct platform_device *pdev)
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dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
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dd->device_config = stm32_dma_slave_config;
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dd->device_terminate_all = stm32_dma_terminate_all;
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dd->device_synchronize = stm32_dma_synchronize;
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dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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@ -1063,6 +1089,7 @@ static int stm32_dma_probe(struct platform_device *pdev)
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
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dd->max_burst = STM32_DMA_MAX_BURST;
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dd->dev = &pdev->dev;
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INIT_LIST_HEAD(&dd->channels);
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