mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-11-28 12:35:22 +08:00
perf tools fixes for v5.19: 2nd batch
- Enable ignore_missing_thread in 'perf stat', enabling counting with '--pid' when threads disappear during counting session setup. - Adjust output data offset for backward compatibility in 'perf inject'. - Fix missing free in copy_kcore_dir() in 'perf inject'. - Fix caching files with a wrong build ID. - Sync drm, cpufeatures, vhost and svn headers with the kernel. Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQR2GiIUctdOfX2qHhGyPKLppCJ+JwUCYridUwAKCRCyPKLppCJ+ JwQXAQCsoW6NcgFW1LOW2XPYQkyhMVmUpDJErqTM9DKHMV2qVAD/dOWvXTff6lh0 ylXTqemsDUX56ATy5CAQKY0w1T3t4QY= =xRzi -----END PGP SIGNATURE----- Merge tag 'perf-tools-fixes-for-v5.19-2022-06-26' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux Pull perf tools fixes from Arnaldo Carvalho de Melo: - Enable ignore_missing_thread in 'perf stat', enabling counting with '--pid' when threads disappear during counting session setup - Adjust output data offset for backward compatibility in 'perf inject' - Fix missing free in copy_kcore_dir() in 'perf inject' - Fix caching files with a wrong build ID - Sync drm, cpufeatures, vhost and svn headers with the kernel * tag 'perf-tools-fixes-for-v5.19-2022-06-26' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: tools headers UAPI: Synch KVM's svm.h header with the kernel tools include UAPI: Sync linux/vhost.h with the kernel sources perf stat: Enable ignore_missing_thread perf inject: Adjust output data offset for backward compatibility perf trace beauty: Fix generation of errno id->str table on ALT Linux perf build-id: Fix caching files with a wrong build ID tools headers cpufeatures: Sync with the kernel sources tools headers UAPI: Sync drm/i915_drm.h with the kernel sources perf inject: Fix missing free in copy_kcore_dir()
This commit is contained in:
Linus Torvalds
commit
893d1eaa56
@ -201,7 +201,7 @@
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#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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/* FREE! ( 7*32+10) */
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#define X86_FEATURE_XCOMPACTED ( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */
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#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
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#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */
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@ -211,7 +211,7 @@
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#define X86_FEATURE_SSBD ( 7*32+17) /* Speculative Store Bypass Disable */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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#define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* "" Fill RSB on context switches */
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/* FREE! ( 7*32+20) */
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#define X86_FEATURE_PERFMON_V2 ( 7*32+20) /* AMD Performance Monitoring Version 2 */
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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@ -238,6 +238,7 @@
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#define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
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#define X86_FEATURE_PVUNLOCK ( 8*32+20) /* "" PV unlock function */
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#define X86_FEATURE_VCPUPREEMPT ( 8*32+21) /* "" PV vcpu_is_preempted function */
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#define X86_FEATURE_TDX_GUEST ( 8*32+22) /* Intel Trust Domain Extensions Guest */
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
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#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
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@ -315,6 +316,7 @@
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#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
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#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
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#define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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@ -405,6 +407,7 @@
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#define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */
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#define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */
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#define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
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#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */
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#define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */
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/*
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@ -62,6 +62,12 @@
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# define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31))
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#endif
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#ifdef CONFIG_INTEL_TDX_GUEST
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# define DISABLE_TDX_GUEST 0
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#else
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# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31))
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#endif
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/*
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* Make sure to add features to the correct mask
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*/
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@ -73,7 +79,7 @@
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#define DISABLED_MASK5 0
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#define DISABLED_MASK6 0
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#define DISABLED_MASK7 (DISABLE_PTI)
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#define DISABLED_MASK8 0
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#define DISABLED_MASK8 (DISABLE_TDX_GUEST)
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#define DISABLED_MASK9 (DISABLE_SGX)
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#define DISABLED_MASK10 0
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#define DISABLED_MASK11 0
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@ -108,6 +108,14 @@
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#define SVM_VMGEXIT_AP_JUMP_TABLE 0x80000005
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#define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0
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#define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1
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#define SVM_VMGEXIT_PSC 0x80000010
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#define SVM_VMGEXIT_GUEST_REQUEST 0x80000011
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#define SVM_VMGEXIT_EXT_GUEST_REQUEST 0x80000012
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#define SVM_VMGEXIT_AP_CREATION 0x80000013
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#define SVM_VMGEXIT_AP_CREATE_ON_INIT 0
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#define SVM_VMGEXIT_AP_CREATE 1
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#define SVM_VMGEXIT_AP_DESTROY 2
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#define SVM_VMGEXIT_HV_FEATURES 0x8000fffd
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#define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff
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/* Exit code reserved for hypervisor/software use */
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@ -218,6 +226,11 @@
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{ SVM_VMGEXIT_NMI_COMPLETE, "vmgexit_nmi_complete" }, \
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{ SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \
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{ SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \
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{ SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \
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{ SVM_VMGEXIT_GUEST_REQUEST, "vmgexit_guest_request" }, \
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{ SVM_VMGEXIT_EXT_GUEST_REQUEST, "vmgexit_ext_guest_request" }, \
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{ SVM_VMGEXIT_AP_CREATION, "vmgexit_ap_creation" }, \
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{ SVM_VMGEXIT_HV_FEATURES, "vmgexit_hypervisor_feature" }, \
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{ SVM_EXIT_ERR, "invalid_guest_state" }
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@ -154,25 +154,77 @@ enum i915_mocs_table_index {
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I915_MOCS_CACHED,
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};
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/*
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/**
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* enum drm_i915_gem_engine_class - uapi engine type enumeration
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*
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* Different engines serve different roles, and there may be more than one
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* engine serving each role. enum drm_i915_gem_engine_class provides a
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* classification of the role of the engine, which may be used when requesting
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* operations to be performed on a certain subset of engines, or for providing
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* information about that group.
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* engine serving each role. This enum provides a classification of the role
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* of the engine, which may be used when requesting operations to be performed
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* on a certain subset of engines, or for providing information about that
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* group.
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*/
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enum drm_i915_gem_engine_class {
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/**
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* @I915_ENGINE_CLASS_RENDER:
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*
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* Render engines support instructions used for 3D, Compute (GPGPU),
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* and programmable media workloads. These instructions fetch data and
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* dispatch individual work items to threads that operate in parallel.
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* The threads run small programs (called "kernels" or "shaders") on
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* the GPU's execution units (EUs).
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*/
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I915_ENGINE_CLASS_RENDER = 0,
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/**
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* @I915_ENGINE_CLASS_COPY:
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*
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* Copy engines (also referred to as "blitters") support instructions
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* that move blocks of data from one location in memory to another,
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* or that fill a specified location of memory with fixed data.
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* Copy engines can perform pre-defined logical or bitwise operations
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* on the source, destination, or pattern data.
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*/
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I915_ENGINE_CLASS_COPY = 1,
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/**
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* @I915_ENGINE_CLASS_VIDEO:
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*
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* Video engines (also referred to as "bit stream decode" (BSD) or
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* "vdbox") support instructions that perform fixed-function media
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* decode and encode.
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*/
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I915_ENGINE_CLASS_VIDEO = 2,
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/**
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* @I915_ENGINE_CLASS_VIDEO_ENHANCE:
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*
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* Video enhancement engines (also referred to as "vebox") support
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* instructions related to image enhancement.
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*/
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I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
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/* should be kept compact */
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/**
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* @I915_ENGINE_CLASS_COMPUTE:
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*
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* Compute engines support a subset of the instructions available
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* on render engines: compute engines support Compute (GPGPU) and
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* programmable media workloads, but do not support the 3D pipeline.
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*/
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I915_ENGINE_CLASS_COMPUTE = 4,
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/* Values in this enum should be kept compact. */
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/**
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* @I915_ENGINE_CLASS_INVALID:
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*
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* Placeholder value to represent an invalid engine class assignment.
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*/
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I915_ENGINE_CLASS_INVALID = -1
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};
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/*
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/**
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* struct i915_engine_class_instance - Engine class/instance identifier
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*
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* There may be more than one engine fulfilling any role within the system.
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* Each engine of a class is given a unique instance number and therefore
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* any engine can be specified by its class:instance tuplet. APIs that allow
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@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
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* for this identification.
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*/
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struct i915_engine_class_instance {
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__u16 engine_class; /* see enum drm_i915_gem_engine_class */
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__u16 engine_instance;
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/**
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* @engine_class:
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*
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* Engine class from enum drm_i915_gem_engine_class
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*/
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__u16 engine_class;
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#define I915_ENGINE_CLASS_INVALID_NONE -1
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#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
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/**
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* @engine_instance:
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*
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* Engine instance.
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*/
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__u16 engine_instance;
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};
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/**
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@ -2657,24 +2720,65 @@ enum drm_i915_perf_record_type {
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DRM_I915_PERF_RECORD_MAX /* non-ABI */
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};
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/*
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/**
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* struct drm_i915_perf_oa_config
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*
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* Structure to upload perf dynamic configuration into the kernel.
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*/
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struct drm_i915_perf_oa_config {
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/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
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/**
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* @uuid:
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*
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* String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
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*/
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char uuid[36];
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/**
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* @n_mux_regs:
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*
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* Number of mux regs in &mux_regs_ptr.
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*/
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__u32 n_mux_regs;
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/**
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* @n_boolean_regs:
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*
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* Number of boolean regs in &boolean_regs_ptr.
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*/
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__u32 n_boolean_regs;
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/**
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* @n_flex_regs:
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*
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* Number of flex regs in &flex_regs_ptr.
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*/
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__u32 n_flex_regs;
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/*
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* These fields are pointers to tuples of u32 values (register address,
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* value). For example the expected length of the buffer pointed by
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* mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
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/**
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* @mux_regs_ptr:
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*
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* Pointer to tuples of u32 values (register address, value) for mux
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* registers. Expected length of buffer is (2 * sizeof(u32) *
|
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* &n_mux_regs).
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*/
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__u64 mux_regs_ptr;
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/**
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* @boolean_regs_ptr:
|
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*
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* Pointer to tuples of u32 values (register address, value) for mux
|
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* registers. Expected length of buffer is (2 * sizeof(u32) *
|
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* &n_boolean_regs).
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*/
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__u64 boolean_regs_ptr;
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/**
|
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* @flex_regs_ptr:
|
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*
|
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* Pointer to tuples of u32 values (register address, value) for mux
|
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* registers. Expected length of buffer is (2 * sizeof(u32) *
|
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* &n_flex_regs).
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*/
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__u64 flex_regs_ptr;
|
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};
|
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@ -2685,12 +2789,24 @@ struct drm_i915_perf_oa_config {
|
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* @data_ptr is also depends on the specific @query_id.
|
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*/
|
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struct drm_i915_query_item {
|
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/** @query_id: The id for this query */
|
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/**
|
||||
* @query_id:
|
||||
*
|
||||
* The id for this query. Currently accepted query IDs are:
|
||||
* - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
|
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* - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
|
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* - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
|
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* - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
|
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* - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
|
||||
* - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
|
||||
*/
|
||||
__u64 query_id;
|
||||
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
|
||||
#define DRM_I915_QUERY_ENGINE_INFO 2
|
||||
#define DRM_I915_QUERY_PERF_CONFIG 3
|
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#define DRM_I915_QUERY_MEMORY_REGIONS 4
|
||||
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
|
||||
#define DRM_I915_QUERY_ENGINE_INFO 2
|
||||
#define DRM_I915_QUERY_PERF_CONFIG 3
|
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#define DRM_I915_QUERY_MEMORY_REGIONS 4
|
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#define DRM_I915_QUERY_HWCONFIG_BLOB 5
|
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#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
/**
|
||||
@ -2706,14 +2822,17 @@ struct drm_i915_query_item {
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
|
||||
* When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
|
||||
*
|
||||
* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
|
||||
* When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
|
||||
* following:
|
||||
*
|
||||
* - DRM_I915_QUERY_PERF_CONFIG_LIST
|
||||
* - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
|
||||
* - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
|
||||
* - %DRM_I915_QUERY_PERF_CONFIG_LIST
|
||||
* - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
|
||||
* - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
|
||||
*
|
||||
* When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
|
||||
* a struct i915_engine_class_instance that references a render engine.
|
||||
*/
|
||||
__u32 flags;
|
||||
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
|
||||
@ -2771,66 +2890,112 @@ struct drm_i915_query {
|
||||
__u64 items_ptr;
|
||||
};
|
||||
|
||||
/*
|
||||
* Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
|
||||
/**
|
||||
* struct drm_i915_query_topology_info
|
||||
*
|
||||
* data: contains the 3 pieces of information :
|
||||
*
|
||||
* - the slice mask with one bit per slice telling whether a slice is
|
||||
* available. The availability of slice X can be queried with the following
|
||||
* formula :
|
||||
*
|
||||
* (data[X / 8] >> (X % 8)) & 1
|
||||
*
|
||||
* - the subslice mask for each slice with one bit per subslice telling
|
||||
* whether a subslice is available. Gen12 has dual-subslices, which are
|
||||
* similar to two gen11 subslices. For gen12, this array represents dual-
|
||||
* subslices. The availability of subslice Y in slice X can be queried
|
||||
* with the following formula :
|
||||
*
|
||||
* (data[subslice_offset +
|
||||
* X * subslice_stride +
|
||||
* Y / 8] >> (Y % 8)) & 1
|
||||
*
|
||||
* - the EU mask for each subslice in each slice with one bit per EU telling
|
||||
* whether an EU is available. The availability of EU Z in subslice Y in
|
||||
* slice X can be queried with the following formula :
|
||||
*
|
||||
* (data[eu_offset +
|
||||
* (X * max_subslices + Y) * eu_stride +
|
||||
* Z / 8] >> (Z % 8)) & 1
|
||||
* Describes slice/subslice/EU information queried by
|
||||
* %DRM_I915_QUERY_TOPOLOGY_INFO
|
||||
*/
|
||||
struct drm_i915_query_topology_info {
|
||||
/*
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u16 flags;
|
||||
|
||||
/**
|
||||
* @max_slices:
|
||||
*
|
||||
* The number of bits used to express the slice mask.
|
||||
*/
|
||||
__u16 max_slices;
|
||||
|
||||
/**
|
||||
* @max_subslices:
|
||||
*
|
||||
* The number of bits used to express the subslice mask.
|
||||
*/
|
||||
__u16 max_subslices;
|
||||
|
||||
/**
|
||||
* @max_eus_per_subslice:
|
||||
*
|
||||
* The number of bits in the EU mask that correspond to a single
|
||||
* subslice's EUs.
|
||||
*/
|
||||
__u16 max_eus_per_subslice;
|
||||
|
||||
/*
|
||||
/**
|
||||
* @subslice_offset:
|
||||
*
|
||||
* Offset in data[] at which the subslice masks are stored.
|
||||
*/
|
||||
__u16 subslice_offset;
|
||||
|
||||
/*
|
||||
/**
|
||||
* @subslice_stride:
|
||||
*
|
||||
* Stride at which each of the subslice masks for each slice are
|
||||
* stored.
|
||||
*/
|
||||
__u16 subslice_stride;
|
||||
|
||||
/*
|
||||
/**
|
||||
* @eu_offset:
|
||||
*
|
||||
* Offset in data[] at which the EU masks are stored.
|
||||
*/
|
||||
__u16 eu_offset;
|
||||
|
||||
/*
|
||||
/**
|
||||
* @eu_stride:
|
||||
*
|
||||
* Stride at which each of the EU masks for each subslice are stored.
|
||||
*/
|
||||
__u16 eu_stride;
|
||||
|
||||
/**
|
||||
* @data:
|
||||
*
|
||||
* Contains 3 pieces of information :
|
||||
*
|
||||
* - The slice mask with one bit per slice telling whether a slice is
|
||||
* available. The availability of slice X can be queried with the
|
||||
* following formula :
|
||||
*
|
||||
* .. code:: c
|
||||
*
|
||||
* (data[X / 8] >> (X % 8)) & 1
|
||||
*
|
||||
* Starting with Xe_HP platforms, Intel hardware no longer has
|
||||
* traditional slices so i915 will always report a single slice
|
||||
* (hardcoded slicemask = 0x1) which contains all of the platform's
|
||||
* subslices. I.e., the mask here does not reflect any of the newer
|
||||
* hardware concepts such as "gslices" or "cslices" since userspace
|
||||
* is capable of inferring those from the subslice mask.
|
||||
*
|
||||
* - The subslice mask for each slice with one bit per subslice telling
|
||||
* whether a subslice is available. Starting with Gen12 we use the
|
||||
* term "subslice" to refer to what the hardware documentation
|
||||
* describes as a "dual-subslices." The availability of subslice Y
|
||||
* in slice X can be queried with the following formula :
|
||||
*
|
||||
* .. code:: c
|
||||
*
|
||||
* (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
|
||||
*
|
||||
* - The EU mask for each subslice in each slice, with one bit per EU
|
||||
* telling whether an EU is available. The availability of EU Z in
|
||||
* subslice Y in slice X can be queried with the following formula :
|
||||
*
|
||||
* .. code:: c
|
||||
*
|
||||
* (data[eu_offset +
|
||||
* (X * max_subslices + Y) * eu_stride +
|
||||
* Z / 8
|
||||
* ] >> (Z % 8)) & 1
|
||||
*/
|
||||
__u8 data[];
|
||||
};
|
||||
|
||||
@ -2951,52 +3116,68 @@ struct drm_i915_query_engine_info {
|
||||
struct drm_i915_engine_info engines[];
|
||||
};
|
||||
|
||||
/*
|
||||
* Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
|
||||
/**
|
||||
* struct drm_i915_query_perf_config
|
||||
*
|
||||
* Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
|
||||
* %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
|
||||
*/
|
||||
struct drm_i915_query_perf_config {
|
||||
union {
|
||||
/*
|
||||
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
|
||||
* this fields to the number of configurations available.
|
||||
/**
|
||||
* @n_configs:
|
||||
*
|
||||
* When &drm_i915_query_item.flags ==
|
||||
* %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
|
||||
* the number of configurations available.
|
||||
*/
|
||||
__u64 n_configs;
|
||||
|
||||
/*
|
||||
* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
|
||||
* i915 will use the value in this field as configuration
|
||||
* identifier to decide what data to write into config_ptr.
|
||||
/**
|
||||
* @config:
|
||||
*
|
||||
* When &drm_i915_query_item.flags ==
|
||||
* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
|
||||
* value in this field as configuration identifier to decide
|
||||
* what data to write into config_ptr.
|
||||
*/
|
||||
__u64 config;
|
||||
|
||||
/*
|
||||
* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
|
||||
* i915 will use the value in this field as configuration
|
||||
* identifier to decide what data to write into config_ptr.
|
||||
/**
|
||||
* @uuid:
|
||||
*
|
||||
* When &drm_i915_query_item.flags ==
|
||||
* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
|
||||
* value in this field as configuration identifier to decide
|
||||
* what data to write into config_ptr.
|
||||
*
|
||||
* String formatted like "%08x-%04x-%04x-%04x-%012x"
|
||||
*/
|
||||
char uuid[36];
|
||||
};
|
||||
|
||||
/*
|
||||
/**
|
||||
* @flags:
|
||||
*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/*
|
||||
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
|
||||
* write an array of __u64 of configuration identifiers.
|
||||
/**
|
||||
* @data:
|
||||
*
|
||||
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
|
||||
* write a struct drm_i915_perf_oa_config. If the following fields of
|
||||
* drm_i915_perf_oa_config are set not set to 0, i915 will write into
|
||||
* the associated pointers the values of submitted when the
|
||||
* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
|
||||
* i915 will write an array of __u64 of configuration identifiers.
|
||||
*
|
||||
* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
|
||||
* i915 will write a struct drm_i915_perf_oa_config. If the following
|
||||
* fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
|
||||
* write into the associated pointers the values of submitted when the
|
||||
* configuration was created :
|
||||
*
|
||||
* - n_mux_regs
|
||||
* - n_boolean_regs
|
||||
* - n_flex_regs
|
||||
* - &drm_i915_perf_oa_config.n_mux_regs
|
||||
* - &drm_i915_perf_oa_config.n_boolean_regs
|
||||
* - &drm_i915_perf_oa_config.n_flex_regs
|
||||
*/
|
||||
__u8 data[];
|
||||
};
|
||||
@ -3134,6 +3315,16 @@ struct drm_i915_query_memory_regions {
|
||||
struct drm_i915_memory_region_info regions[];
|
||||
};
|
||||
|
||||
/**
|
||||
* DOC: GuC HWCONFIG blob uAPI
|
||||
*
|
||||
* The GuC produces a blob with information about the current device.
|
||||
* i915 reads this blob from GuC and makes it available via this uAPI.
|
||||
*
|
||||
* The format and meaning of the blob content are documented in the
|
||||
* Programmer's Reference Manual.
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
|
||||
* extension support using struct i915_user_extension.
|
||||
|
||||
@ -89,11 +89,6 @@
|
||||
|
||||
/* Set or get vhost backend capability */
|
||||
|
||||
/* Use message type V2 */
|
||||
#define VHOST_BACKEND_F_IOTLB_MSG_V2 0x1
|
||||
/* IOTLB can accept batching hints */
|
||||
#define VHOST_BACKEND_F_IOTLB_BATCH 0x2
|
||||
|
||||
#define VHOST_SET_BACKEND_FEATURES _IOW(VHOST_VIRTIO, 0x25, __u64)
|
||||
#define VHOST_GET_BACKEND_FEATURES _IOR(VHOST_VIRTIO, 0x26, __u64)
|
||||
|
||||
@ -150,11 +145,30 @@
|
||||
/* Get the valid iova range */
|
||||
#define VHOST_VDPA_GET_IOVA_RANGE _IOR(VHOST_VIRTIO, 0x78, \
|
||||
struct vhost_vdpa_iova_range)
|
||||
|
||||
/* Get the config size */
|
||||
#define VHOST_VDPA_GET_CONFIG_SIZE _IOR(VHOST_VIRTIO, 0x79, __u32)
|
||||
|
||||
/* Get the count of all virtqueues */
|
||||
#define VHOST_VDPA_GET_VQS_COUNT _IOR(VHOST_VIRTIO, 0x80, __u32)
|
||||
|
||||
/* Get the number of virtqueue groups. */
|
||||
#define VHOST_VDPA_GET_GROUP_NUM _IOR(VHOST_VIRTIO, 0x81, __u32)
|
||||
|
||||
/* Get the number of address spaces. */
|
||||
#define VHOST_VDPA_GET_AS_NUM _IOR(VHOST_VIRTIO, 0x7A, unsigned int)
|
||||
|
||||
/* Get the group for a virtqueue: read index, write group in num,
|
||||
* The virtqueue index is stored in the index field of
|
||||
* vhost_vring_state. The group for this specific virtqueue is
|
||||
* returned via num field of vhost_vring_state.
|
||||
*/
|
||||
#define VHOST_VDPA_GET_VRING_GROUP _IOWR(VHOST_VIRTIO, 0x7B, \
|
||||
struct vhost_vring_state)
|
||||
/* Set the ASID for a virtqueue group. The group index is stored in
|
||||
* the index field of vhost_vring_state, the ASID associated with this
|
||||
* group is stored at num field of vhost_vring_state.
|
||||
*/
|
||||
#define VHOST_VDPA_SET_GROUP_ASID _IOW(VHOST_VIRTIO, 0x7C, \
|
||||
struct vhost_vring_state)
|
||||
|
||||
#endif
|
||||
|
||||
@ -891,7 +891,9 @@ static int copy_kcore_dir(struct perf_inject *inject)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
pr_debug("%s\n", cmd);
|
||||
return system(cmd);
|
||||
ret = system(cmd);
|
||||
free(cmd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int output_fd(struct perf_inject *inject)
|
||||
@ -916,7 +918,7 @@ static int __cmd_inject(struct perf_inject *inject)
|
||||
inject->tool.tracing_data = perf_event__repipe_tracing_data;
|
||||
}
|
||||
|
||||
output_data_offset = session->header.data_offset;
|
||||
output_data_offset = perf_session__data_offset(session->evlist);
|
||||
|
||||
if (inject->build_id_all) {
|
||||
inject->tool.mmap = perf_event__repipe_buildid_mmap;
|
||||
|
||||
@ -2586,6 +2586,8 @@ int cmd_stat(int argc, const char **argv)
|
||||
if (evlist__initialize_ctlfd(evsel_list, stat_config.ctl_fd, stat_config.ctl_fd_ack))
|
||||
goto out;
|
||||
|
||||
/* Enable ignoring missing threads when -p option is defined. */
|
||||
evlist__first(evsel_list)->ignore_missing_thread = target.pid;
|
||||
status = 0;
|
||||
for (run_idx = 0; forever || run_idx < stat_config.run_count; run_idx++) {
|
||||
if (stat_config.run_count != 1 && verbose > 0)
|
||||
|
||||
@ -33,23 +33,13 @@ create_errno_lookup_func()
|
||||
local arch=$(arch_string "$1")
|
||||
local nr name
|
||||
|
||||
cat <<EoFuncBegin
|
||||
static const char *errno_to_name__$arch(int err)
|
||||
{
|
||||
switch (err) {
|
||||
EoFuncBegin
|
||||
printf "static const char *errno_to_name__%s(int err)\n{\n\tswitch (err) {\n" $arch
|
||||
|
||||
while read name nr; do
|
||||
printf '\tcase %d: return "%s";\n' $nr $name
|
||||
done
|
||||
|
||||
cat <<EoFuncEnd
|
||||
default:
|
||||
return "(unknown)";
|
||||
}
|
||||
}
|
||||
|
||||
EoFuncEnd
|
||||
printf '\tdefault: return "(unknown)";\n\t}\n}\n'
|
||||
}
|
||||
|
||||
process_arch()
|
||||
|
||||
@ -872,6 +872,30 @@ out_free:
|
||||
return err;
|
||||
}
|
||||
|
||||
static int filename__read_build_id_ns(const char *filename,
|
||||
struct build_id *bid,
|
||||
struct nsinfo *nsi)
|
||||
{
|
||||
struct nscookie nsc;
|
||||
int ret;
|
||||
|
||||
nsinfo__mountns_enter(nsi, &nsc);
|
||||
ret = filename__read_build_id(filename, bid);
|
||||
nsinfo__mountns_exit(&nsc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool dso__build_id_mismatch(struct dso *dso, const char *name)
|
||||
{
|
||||
struct build_id bid;
|
||||
|
||||
if (filename__read_build_id_ns(name, &bid, dso->nsinfo) < 0)
|
||||
return false;
|
||||
|
||||
return !dso__build_id_equal(dso, &bid);
|
||||
}
|
||||
|
||||
static int dso__cache_build_id(struct dso *dso, struct machine *machine,
|
||||
void *priv __maybe_unused)
|
||||
{
|
||||
@ -886,6 +910,10 @@ static int dso__cache_build_id(struct dso *dso, struct machine *machine,
|
||||
is_kallsyms = true;
|
||||
name = machine->mmap_name;
|
||||
}
|
||||
|
||||
if (!is_kallsyms && dso__build_id_mismatch(dso, name))
|
||||
return 0;
|
||||
|
||||
return build_id_cache__add_b(&dso->bid, name, dso->nsinfo,
|
||||
is_kallsyms, is_vdso);
|
||||
}
|
||||
|
||||
@ -3686,6 +3686,20 @@ int perf_session__write_header(struct perf_session *session,
|
||||
return perf_session__do_write_header(session, evlist, fd, at_exit, NULL);
|
||||
}
|
||||
|
||||
size_t perf_session__data_offset(const struct evlist *evlist)
|
||||
{
|
||||
struct evsel *evsel;
|
||||
size_t data_offset;
|
||||
|
||||
data_offset = sizeof(struct perf_file_header);
|
||||
evlist__for_each_entry(evlist, evsel) {
|
||||
data_offset += evsel->core.ids * sizeof(u64);
|
||||
}
|
||||
data_offset += evlist->core.nr_entries * sizeof(struct perf_file_attr);
|
||||
|
||||
return data_offset;
|
||||
}
|
||||
|
||||
int perf_session__inject_header(struct perf_session *session,
|
||||
struct evlist *evlist,
|
||||
int fd,
|
||||
|
||||
@ -136,6 +136,8 @@ int perf_session__inject_header(struct perf_session *session,
|
||||
int fd,
|
||||
struct feat_copier *fc);
|
||||
|
||||
size_t perf_session__data_offset(const struct evlist *evlist);
|
||||
|
||||
void perf_header__set_feat(struct perf_header *header, int feat);
|
||||
void perf_header__clear_feat(struct perf_header *header, int feat);
|
||||
bool perf_header__has_feat(const struct perf_header *header, int feat);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user