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phy: qcom-qusb2: Add support for runtime PM
Disable clocks and enable DP/DM wakeup interrupts when suspending PHY. Core driver should notify speed to PHY driver to enable appropriate DP/DM wakeup interrupts polarity in suspend state. Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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@ -56,6 +56,18 @@
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#define PHY_CLK_SCHEME_SEL BIT(0)
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/* QUSB2PHY_INTR_CTRL register bits */
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#define DMSE_INTR_HIGH_SEL BIT(4)
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#define DPSE_INTR_HIGH_SEL BIT(3)
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#define CHG_DET_INTR_EN BIT(2)
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#define DMSE_INTR_EN BIT(1)
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#define DPSE_INTR_EN BIT(0)
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/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
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#define CORE_PLL_EN_FROM_RESET BIT(4)
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#define CORE_RESET BIT(5)
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#define CORE_RESET_MUX BIT(6)
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#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
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#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
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#define QUSB2PHY_PLL_CMODE 0x2c
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@ -93,6 +105,7 @@ struct qusb2_phy_init_tbl {
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/* set of registers with offsets different per-PHY */
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enum qusb2phy_reg_layout {
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QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
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QUSB2PHY_PLL_STATUS,
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QUSB2PHY_PORT_TUNE1,
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QUSB2PHY_PORT_TUNE2,
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@ -112,8 +125,10 @@ static const unsigned int msm8996_regs_layout[] = {
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[QUSB2PHY_PORT_TUNE3] = 0x88,
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[QUSB2PHY_PORT_TUNE4] = 0x8c,
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[QUSB2PHY_PORT_TUNE5] = 0x90,
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[QUSB2PHY_PORT_TEST1] = 0xb8,
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[QUSB2PHY_PORT_TEST2] = 0x9c,
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[QUSB2PHY_PORT_POWERDOWN] = 0xb4,
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[QUSB2PHY_INTR_CTRL] = 0xbc,
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};
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static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
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@ -133,14 +148,17 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
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};
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static const unsigned int qusb2_v2_regs_layout[] = {
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[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
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[QUSB2PHY_PLL_STATUS] = 0x1a0,
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[QUSB2PHY_PORT_TUNE1] = 0x240,
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[QUSB2PHY_PORT_TUNE2] = 0x244,
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[QUSB2PHY_PORT_TUNE3] = 0x248,
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[QUSB2PHY_PORT_TUNE4] = 0x24c,
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[QUSB2PHY_PORT_TUNE5] = 0x250,
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[QUSB2PHY_PORT_TEST1] = 0x254,
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[QUSB2PHY_PORT_TEST2] = 0x258,
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[QUSB2PHY_PORT_POWERDOWN] = 0x210,
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[QUSB2PHY_INTR_CTRL] = 0x230,
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};
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static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
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@ -175,12 +193,16 @@ struct qusb2_phy_cfg {
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const unsigned int *regs;
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unsigned int mask_core_ready;
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unsigned int disable_ctrl;
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unsigned int autoresume_en;
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/* true if PHY has PLL_TEST register to select clk_scheme */
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bool has_pll_test;
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/* true if TUNE1 register must be updated by fused value, else TUNE2 */
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bool update_tune1_with_efuse;
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/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
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bool has_pll_override;
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};
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static const struct qusb2_phy_cfg msm8996_phy_cfg = {
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@ -191,6 +213,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
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.has_pll_test = true,
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.disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
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.mask_core_ready = PLL_LOCKED,
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.autoresume_en = BIT(3),
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};
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static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
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@ -201,6 +224,8 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
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.disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
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POWER_DOWN),
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.mask_core_ready = CORE_READY_STATUS,
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.has_pll_override = true,
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.autoresume_en = BIT(0),
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};
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static const char * const qusb2_phy_vreg_names[] = {
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@ -226,6 +251,8 @@ static const char * const qusb2_phy_vreg_names[] = {
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*
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* @cfg: phy config data
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* @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
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* @phy_initialized: indicate if PHY has been initialized
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* @mode: current PHY mode
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*/
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struct qusb2_phy {
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struct phy *phy;
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@ -242,6 +269,8 @@ struct qusb2_phy {
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const struct qusb2_phy_cfg *cfg;
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bool has_se_clk_scheme;
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bool phy_initialized;
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enum phy_mode mode;
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};
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static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
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@ -317,6 +346,133 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
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}
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static int qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode)
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{
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struct qusb2_phy *qphy = phy_get_drvdata(phy);
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qphy->mode = mode;
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return 0;
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}
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static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
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{
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struct qusb2_phy *qphy = dev_get_drvdata(dev);
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const struct qusb2_phy_cfg *cfg = qphy->cfg;
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u32 intr_mask;
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dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
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if (!qphy->phy_initialized) {
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dev_vdbg(dev, "PHY not initialized, bailing out\n");
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return 0;
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}
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/*
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* Enable DP/DM interrupts to detect line state changes based on current
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* speed. In other words, enable the triggers _opposite_ of what the
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* current D+/D- levels are e.g. if currently D+ high, D- low
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* (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
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*/
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intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
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switch (qphy->mode) {
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case PHY_MODE_USB_HOST_HS:
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case PHY_MODE_USB_HOST_FS:
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case PHY_MODE_USB_DEVICE_HS:
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case PHY_MODE_USB_DEVICE_FS:
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intr_mask |= DMSE_INTR_HIGH_SEL;
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break;
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case PHY_MODE_USB_HOST_LS:
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case PHY_MODE_USB_DEVICE_LS:
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intr_mask |= DPSE_INTR_HIGH_SEL;
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break;
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default:
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/* No device connected, enable both DP/DM high interrupt */
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intr_mask |= DMSE_INTR_HIGH_SEL;
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intr_mask |= DPSE_INTR_HIGH_SEL;
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break;
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}
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writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
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/* hold core PLL into reset */
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if (cfg->has_pll_override) {
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qusb2_setbits(qphy->base,
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cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
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CORE_PLL_EN_FROM_RESET | CORE_RESET |
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CORE_RESET_MUX);
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}
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/* enable phy auto-resume only if device is connected on bus */
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if (qphy->mode != PHY_MODE_INVALID) {
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qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
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cfg->autoresume_en);
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/* Autoresume bit has to be toggled in order to enable it */
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qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
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cfg->autoresume_en);
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}
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if (!qphy->has_se_clk_scheme)
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clk_disable_unprepare(qphy->ref_clk);
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clk_disable_unprepare(qphy->cfg_ahb_clk);
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clk_disable_unprepare(qphy->iface_clk);
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return 0;
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}
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static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
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{
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struct qusb2_phy *qphy = dev_get_drvdata(dev);
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const struct qusb2_phy_cfg *cfg = qphy->cfg;
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int ret;
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dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
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if (!qphy->phy_initialized) {
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dev_vdbg(dev, "PHY not initialized, bailing out\n");
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return 0;
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}
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ret = clk_prepare_enable(qphy->iface_clk);
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if (ret) {
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dev_err(dev, "failed to enable iface_clk, %d\n", ret);
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return ret;
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}
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ret = clk_prepare_enable(qphy->cfg_ahb_clk);
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if (ret) {
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dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
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goto disable_iface_clk;
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}
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if (!qphy->has_se_clk_scheme) {
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clk_prepare_enable(qphy->ref_clk);
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if (ret) {
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dev_err(dev, "failed to enable ref clk, %d\n", ret);
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goto disable_ahb_clk;
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}
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}
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writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
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/* bring core PLL out of reset */
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if (cfg->has_pll_override) {
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qusb2_clrbits(qphy->base,
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cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
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CORE_RESET | CORE_RESET_MUX);
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}
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return 0;
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disable_ahb_clk:
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clk_disable_unprepare(qphy->cfg_ahb_clk);
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disable_iface_clk:
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clk_disable_unprepare(qphy->iface_clk);
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return ret;
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}
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static int qusb2_phy_init(struct phy *phy)
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{
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struct qusb2_phy *qphy = phy_get_drvdata(phy);
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@ -441,6 +597,7 @@ static int qusb2_phy_init(struct phy *phy)
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ret = -EBUSY;
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goto disable_ref_clk;
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}
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qphy->phy_initialized = true;
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return 0;
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@ -477,12 +634,15 @@ static int qusb2_phy_exit(struct phy *phy)
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regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
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qphy->phy_initialized = false;
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return 0;
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}
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static const struct phy_ops qusb2_phy_gen_ops = {
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.init = qusb2_phy_init,
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.exit = qusb2_phy_exit,
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.set_mode = qusb2_phy_set_mode,
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.owner = THIS_MODULE,
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};
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@ -498,6 +658,11 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
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};
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MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
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static const struct dev_pm_ops qusb2_phy_pm_ops = {
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SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
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qusb2_phy_runtime_resume, NULL)
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};
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static int qusb2_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -575,11 +740,19 @@ static int qusb2_phy_probe(struct platform_device *pdev)
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qphy->cell = NULL;
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dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
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}
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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/*
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* Prevent runtime pm from being ON by default. Users can enable
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* it using power/control in sysfs.
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*/
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pm_runtime_forbid(dev);
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generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
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if (IS_ERR(generic_phy)) {
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ret = PTR_ERR(generic_phy);
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dev_err(dev, "failed to create phy, %d\n", ret);
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pm_runtime_disable(dev);
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return ret;
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}
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qphy->phy = generic_phy;
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@ -590,6 +763,8 @@ static int qusb2_phy_probe(struct platform_device *pdev)
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (!IS_ERR(phy_provider))
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dev_info(dev, "Registered Qcom-QUSB2 phy\n");
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else
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pm_runtime_disable(dev);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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@ -598,6 +773,7 @@ static struct platform_driver qusb2_phy_driver = {
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.probe = qusb2_phy_probe,
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.driver = {
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.name = "qcom-qusb2-phy",
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.pm = &qusb2_phy_pm_ops,
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.of_match_table = qusb2_phy_of_match_table,
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},
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};
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