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Blackfin: increase default async timings for parallel flashes
The default async timings are a little too fast for the parallel flash that is attached by default to the async banks. So slow things down a bit so accessing the hardware is stable. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -358,9 +358,9 @@ CONFIG_C_AMBEN_ALL=y
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# EBIU_AMBCTL Control
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#
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CONFIG_BANK_0=0x7BB0
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CONFIG_BANK_1=0x5554
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CONFIG_BANK_1=0x7BB0
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CONFIG_BANK_2=0x7BB0
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CONFIG_BANK_3=0xFFC0
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CONFIG_BANK_3=0x99B2
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#
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# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
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@ -359,9 +359,9 @@ CONFIG_C_AMBEN_ALL=y
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# EBIU_AMBCTL Control
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#
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CONFIG_BANK_0=0x7BB0
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CONFIG_BANK_1=0x5554
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CONFIG_BANK_1=0x7BB0
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CONFIG_BANK_2=0x7BB0
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CONFIG_BANK_3=0xFFC0
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CONFIG_BANK_3=0x99B2
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#
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# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
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@ -363,9 +363,9 @@ CONFIG_C_AMBEN_ALL=y
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# EBIU_AMBCTL Control
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#
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CONFIG_BANK_0=0x7BB0
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CONFIG_BANK_1=0x5554
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CONFIG_BANK_1=0x7BB0
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CONFIG_BANK_2=0x7BB0
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CONFIG_BANK_3=0xFFC0
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CONFIG_BANK_3=0x99B2
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#
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# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
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@ -400,7 +400,7 @@ CONFIG_C_AMBEN_ALL=y
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# EBIU_AMBCTL Control
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#
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CONFIG_BANK_0=0x7BB0
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CONFIG_BANK_1=0x5554
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CONFIG_BANK_1=0x7BB0
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CONFIG_BANK_2=0x7BB0
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CONFIG_BANK_3=0x99B2
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CONFIG_EBIU_MBSCTLVAL=0x0
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