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pwm: mtk-disp: Implement atomic API .apply()
Switch the driver to support the .apply() method. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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d7a4e58258
commit
888a623db5
@ -47,6 +47,7 @@ struct mtk_disp_pwm {
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struct clk *clk_main;
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struct clk *clk_mm;
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void __iomem *base;
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bool enabled;
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};
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static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
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@ -66,26 +67,46 @@ static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
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writel(value, address);
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}
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static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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u32 clk_div, period, high_width, value;
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u64 div, rate;
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int err;
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if (state->polarity != PWM_POLARITY_NORMAL)
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return -EINVAL;
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if (!state->enabled) {
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mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
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0x0);
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if (mdp->enabled) {
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clk_disable_unprepare(mdp->clk_mm);
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clk_disable_unprepare(mdp->clk_main);
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}
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mdp->enabled = false;
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return 0;
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}
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if (!mdp->enabled) {
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err = clk_prepare_enable(mdp->clk_main);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
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dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
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ERR_PTR(err));
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return err;
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}
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err = clk_prepare_enable(mdp->clk_mm);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
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dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
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ERR_PTR(err));
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clk_disable_unprepare(mdp->clk_main);
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return err;
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}
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}
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/*
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* Find period, high_width and clk_div to suit duty_ns and period_ns.
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@ -98,20 +119,22 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
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*/
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rate = clk_get_rate(mdp->clk_main);
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clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
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clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >>
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PWM_PERIOD_BIT_WIDTH;
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if (clk_div > PWM_CLKDIV_MAX) {
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if (!mdp->enabled) {
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clk_disable_unprepare(mdp->clk_mm);
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clk_disable_unprepare(mdp->clk_main);
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}
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return -EINVAL;
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}
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div = NSEC_PER_SEC * (clk_div + 1);
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period = div64_u64(rate * period_ns, div);
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period = div64_u64(rate * state->period, div);
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if (period > 0)
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period--;
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high_width = div64_u64(rate * duty_ns, div);
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high_width = div64_u64(rate * state->duty_cycle, div);
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value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
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mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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@ -141,51 +164,15 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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mdp->data->con0_sel);
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}
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clk_disable_unprepare(mdp->clk_mm);
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clk_disable_unprepare(mdp->clk_main);
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return 0;
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}
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static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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int err;
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err = clk_prepare_enable(mdp->clk_main);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
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return err;
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}
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err = clk_prepare_enable(mdp->clk_mm);
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if (err < 0) {
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dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
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clk_disable_unprepare(mdp->clk_main);
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return err;
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}
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mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
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mdp->data->enable_mask);
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mdp->enabled = true;
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return 0;
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}
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static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
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0x0);
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clk_disable_unprepare(mdp->clk_mm);
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clk_disable_unprepare(mdp->clk_main);
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}
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static const struct pwm_ops mtk_disp_pwm_ops = {
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.config = mtk_disp_pwm_config,
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.enable = mtk_disp_pwm_enable,
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.disable = mtk_disp_pwm_disable,
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.apply = mtk_disp_pwm_apply,
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.owner = THIS_MODULE,
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};
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