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mtd: nand: mtk: disable ecc irq when writing page with hwecc

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Currently, ecc encode irq is enabled when writing page with hwecc, but
we actually do not wait for this irq done. Because NFI and ECC work in
parallel, nfi irq and ecc irq almost come together.

Now, there are two steps to check whether page data are totally written.
First, wait for nfi irq INTR_AHB_DONE. This is to ensure all data
in RAM are received by NFI.
Second, polling the register NFI_ADDRCNTR till all data include ecc
parity data runtime generated by ECC are sent to NAND device.

So, it is redunant to enable ecc irq without waiting for it.

Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
This commit is contained in:
Xiaolei Li 2017-06-23 15:12:25 +08:00 committed by Boris Brezillon
parent 188986c70e
commit 8840431255
1 changed files with 12 additions and 10 deletions
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22
drivers/mtd/nand/mtk_ecc.c
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@ -276,16 +276,18 @@ int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
if (ret) if (ret)
return ret; return ret;
init_completion(&ecc->done); if (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {
reg_val = ECC_IRQ_EN; init_completion(&ecc->done);
/* reg_val = ECC_IRQ_EN;
* For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it /*
* means this chip can only generate one ecc irq during page * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
* read / write. If is 0, generate one ecc irq each ecc step. * means this chip can only generate one ecc irq during page
*/ * read / write. If is 0, generate one ecc irq each ecc step.
if ((ecc->caps->pg_irq_sel) && (config->mode == ECC_NFI_MODE)) */
reg_val |= ECC_PG_IRQ_SEL; if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
writew(reg_val, ecc->regs + ECC_IRQ_REG(op)); reg_val |= ECC_PG_IRQ_SEL;
writew(reg_val, ecc->regs + ECC_IRQ_REG(op));
}
writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op)); writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));