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dts part of core suspend support and limiting of rk3288

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sd-card clockspeed to 150mhz
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJUwBx+AAoJEPOmecmc0R2BchUH/28i49EtgL/9L6KYSY8AWb6L
 Cz/msQL88xsy+zS9mGYRb9qi39SpOMS70XWUvVGp939llxzTMvP8/0NYmH6uCxOi
 f7Wjf8vXlhGR01Y9S3cOsL4D7V9+4qSQVzQ/rIFpcR32OaIzN78UuSuqDnAb27/x
 CzaAxol8zM+XxfdxLgWChVJaTPT3WyGC2pUAmzm+2dKviTWV2CoAqavuiWuyqj26
 i0HJHG6dDNfgCt11ScSqwqVLgpQ+cQAQZ1xk4et/Skk/tXz1OCtctQnevFu9ClT5
 MeTnAZvKuNDwmyWMo2V9q1d9DS1s9UY+yXBKRBaF65I+Rmzd94NGxcM7B/NVgCE=
 =C1qi
 -----END PGP SIGNATURE-----

Merge tag 'v3.20-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Merge "ARM: rockchip: soc updates for 3.20" [sic!] from Heiko Stübner:

dts part of core suspend support and limiting of rk3288
sd-card clockspeed to 150mhz

* tag 'v3.20-rockchip-dts1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: add suspend settings for rk3288-evb-rk808
  ARM: dts: rockchip: add RK3288 suspend support
  ARM: dts: rockchip: set dw_mmc max-freq 150Mhz

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2015-01-23 14:06:25 -08:00
commit 8739f728db
2 changed files with 79 additions and 1 deletions
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53
arch/arm/boot/dts/rk3288-evb-rk808.dts
View File

@ -31,7 +31,7 @@
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;
pinctrl-0 = <&pmic_int &global_pwroff>;
rockchip,system-power-controller;
wakeup-source;
#clock-cells = <1>;
@ -50,6 +50,9 @@
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
regulator-name = "vdd_arm";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
@ -58,12 +61,19 @@
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-name = "vdd_gpu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
@ -72,6 +82,10 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_io";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vccio_pmu: LDO_REG1 {
@ -80,6 +94,10 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_tp: LDO_REG2 {
@ -88,6 +106,9 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_tp";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
@ -96,6 +117,10 @@
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd_10";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc18_lcd: LDO_REG4 {
@ -104,6 +129,10 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc18_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vccio_sd: LDO_REG5 {
@ -112,6 +141,10 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd10_lcd: LDO_REG6 {
@ -120,6 +153,10 @@
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-name = "vdd10_lcd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vcc_18: LDO_REG7 {
@ -128,6 +165,10 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_18";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcca_codec: LDO_REG8 {
@ -136,18 +177,28 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_codec";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_wl: SWITCH_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_wl";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_lcd: SWITCH_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vcc_lcd";
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
};

27
arch/arm/boot/dts/rk3288.dtsi
View File

@ -151,6 +151,7 @@
sdmmc: dwmmc@ff0c0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@ -161,6 +162,7 @@
sdio0: dwmmc@ff0d0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@ -171,6 +173,7 @@
sdio1: dwmmc@ff0e0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@ -181,6 +184,7 @@
emmc: dwmmc@ff0f0000 {
compatible = "rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
clock-names = "biu", "ciu";
fifo-depth = <0x100>;
@ -502,6 +506,11 @@
};
};
sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
reg = <0xff720000 0x1000>;
};
pmu: power-management@ff730000 {
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
@ -725,6 +734,24 @@
bias-disable;
};
sleep {
global_pwroff: global-pwroff {
rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
};
ddr0_retention: ddr0-retention {
rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
};
ddr1_retention: ddr1-retention {
rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,