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drm/i915: Split Pineview device info into desktop and mobile
This allows the IS_PINEVIEW_<G|M> macros to be removed and avoid duplication of device ids already defined in i915_pciids.h. !IS_MOBILE check can be used in place of existing IS_PINEVIEW_G call sites. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190326074057.27833-2-tvrtko.ursulin@linux.intel.com
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@ -525,7 +525,8 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
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INTEL_I945G_IDS(&gen3_early_ops),
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INTEL_I945GM_IDS(&gen3_early_ops),
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INTEL_VLV_IDS(&gen6_early_ops),
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INTEL_PINEVIEW_IDS(&gen3_early_ops),
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INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
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INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
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INTEL_I965G_IDS(&gen3_early_ops),
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INTEL_G33_IDS(&gen3_early_ops),
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INTEL_I965GM_IDS(&gen3_early_ops),
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@ -2317,8 +2317,6 @@ static inline unsigned int i915_sg_segment_size(void)
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#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
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#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
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#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
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#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
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#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
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#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
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#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
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#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
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@ -257,7 +257,14 @@ static const struct intel_device_info intel_g33_info = {
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.display.has_overlay = 1,
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};
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static const struct intel_device_info intel_pineview_info = {
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static const struct intel_device_info intel_pineview_g_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_PINEVIEW),
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.display.has_hotplug = 1,
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.display.has_overlay = 1,
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};
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static const struct intel_device_info intel_pineview_m_info = {
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GEN3_FEATURES,
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PLATFORM(INTEL_PINEVIEW),
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.is_mobile = 1,
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@ -761,7 +768,8 @@ static const struct pci_device_id pciidlist[] = {
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INTEL_I965GM_IDS(&intel_i965gm_info),
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INTEL_GM45_IDS(&intel_gm45_info),
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INTEL_G45_IDS(&intel_g45_info),
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INTEL_PINEVIEW_IDS(&intel_pineview_info),
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INTEL_PINEVIEW_G_IDS(&intel_pineview_g_info),
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INTEL_PINEVIEW_M_IDS(&intel_pineview_m_info),
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INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
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INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
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INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
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@ -850,7 +850,7 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc)
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u32 reg;
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unsigned int wm;
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latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
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latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
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dev_priv->is_ddr3,
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dev_priv->fsb_freq,
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dev_priv->mem_freq);
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@ -9589,7 +9589,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
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dev_priv->display.initial_watermarks = g4x_initial_watermarks;
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dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
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} else if (IS_PINEVIEW(dev_priv)) {
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if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
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if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
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dev_priv->is_ddr3,
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dev_priv->fsb_freq,
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dev_priv->mem_freq)) {
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@ -108,8 +108,10 @@
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INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
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INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
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#define INTEL_PINEVIEW_IDS(info) \
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INTEL_VGA_DEVICE(0xa001, info), \
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#define INTEL_PINEVIEW_G_IDS(info) \
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INTEL_VGA_DEVICE(0xa001, info)
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#define INTEL_PINEVIEW_M_IDS(info) \
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INTEL_VGA_DEVICE(0xa011, info)
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#define INTEL_IRONLAKE_D_IDS(info) \
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