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Devicetree updates for v5.19:

Browse Source 
Bindings:
 - Convert smsc,lan91c111, qcom,spi-qup, qcom,msm-uartdm, qcom,i2c-qup,
   qcom,gsbi, i2c-mt65xx, TI wkup_m3_ipc (and new props), qcom,smp2p, TI
   timer, Mediatek gnss, Mediatek topckgen, Mediatek apmixedsys, Mediatek
   infracfg, fsl,ls-extirq, fsl,layerscape-dcfg, QCom PMIC SPMI,
   rda,8810pl-timer, Xilinx zynqmp_ipi, uniphier-pcie, and Ilitek
   touchscreen controllers
 
 - Convert various Arm Ltd peripheral IP bindings to schemas
 
 - New bindings for Menlo board CPLD, DH electronics board CPLD,
   Qualcomm Geni based QUP I2C, Renesas RZ/G2UL OSTM, Broafcom BCM4751
   GNSS, MT6360 PMIC, ASIX USB Ethernet controllers, and Microchip/SMSC
   LAN95xx USB Ethernet controllers
 
 - Add vendor prefix for Enclustra
 
 - Add various compatible string additions
 
 - Various example fixes and cleanups
 
 - Remove unused hisilicon,hi6220-reset binding
 
 - Treewide fix properties missing type definition
 
 - Drop some empty and unreferenced .txt bindings
 
 - Documentation improvements for writing schemas
 
 DT driver core:
 - Drop static IRQ resources for DT platform devices as IRQ setup is
   dynamic and drivers have all been converted to use platform_get_irq()
   and friends
 
 - Rework memory allocations and frees for overlays
 
 - Continue overlay notifier callbacks on successful calls and add
   unittests
 
 - Handle 'interrupts-extended' in early DT IRQ setup
 
 - Fix of_property_read_string() errors to match documentation
 
 - Ignore disabled nodes in FDT API calls
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Merge tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert smsc,lan91c111, qcom,spi-qup, qcom,msm-uartdm,
     qcom,i2c-qup, qcom,gsbi, i2c-mt65xx, TI wkup_m3_ipc (and new
     props), qcom,smp2p, TI timer, Mediatek gnss, Mediatek topckgen,
     Mediatek apmixedsys, Mediatek infracfg, fsl,ls-extirq,
     fsl,layerscape-dcfg, QCom PMIC SPMI, rda,8810pl-timer, Xilinx
     zynqmp_ipi, uniphier-pcie, and Ilitek touchscreen controllers

   - Convert various Arm Ltd peripheral IP bindings to schemas

   - New bindings for Menlo board CPLD, DH electronics board CPLD,
     Qualcomm Geni based QUP I2C, Renesas RZ/G2UL OSTM, Broafcom BCM4751
     GNSS, MT6360 PMIC, ASIX USB Ethernet controllers, and
     Microchip/SMSC LAN95xx USB Ethernet controllers

   - Add vendor prefix for Enclustra

   - Add various compatible string additions

   - Various example fixes and cleanups

   - Remove unused hisilicon,hi6220-reset binding

   - Treewide fix properties missing type definition

   - Drop some empty and unreferenced .txt bindings

   - Documentation improvements for writing schemas

  DT driver core:

   - Drop static IRQ resources for DT platform devices as IRQ setup is
     dynamic and drivers have all been converted to use
     platform_get_irq() and friends

   - Rework memory allocations and frees for overlays

   - Continue overlay notifier callbacks on successful calls and add
     unittests

   - Handle 'interrupts-extended' in early DT IRQ setup

   - Fix of_property_read_string() errors to match documentation

   - Ignore disabled nodes in FDT API calls"

* tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (86 commits)
  of/irq: fix typo in comment
  dt-bindings: Fix properties without any type
  Revert "dt-bindings: mailbox: qcom-ipcc: add missing properties into example"
  dt-bindings: input: touchscreen: ilitek_ts_i2c: Absorb ili2xxx bindings
  dt-bindings: timer: samsung,exynos4210-mct: define strict clock order
  dt-bindings: timer: samsung,exynos4210-mct: drop unneeded minItems
  dt-bindings: timer: cdns,ttc: drop unneeded minItems
  dt-bindings: mailbox: zynqmp_ipi: convert to yaml
  dt-bindings: usb: ci-hdrc-usb2: fix node node for ethernet controller
  dt-bindings: net: add schema for Microchip/SMSC LAN95xx USB Ethernet controllers
  dt-bindings: net: add schema for ASIX USB Ethernet controllers
  of/fdt: Ignore disabled memory nodes
  dt-bindings: arm: fix typos in compatible
  dt-bindings: mfd: Add bindings child nodes for the Mediatek MT6360
  dt-bindings: display: convert Arm Komeda to DT schema
  dt-bindings: display: convert Arm Mali-DP to DT schema
  dt-bindings: display: convert Arm HDLCD to DT schema
  dt-bindings: display: convert PL110/PL111 to DT schema
  dt-bindings: arm: convert vexpress-config to DT schema
  dt-bindings: arm: convert vexpress-sysregs to DT schema
  ...
This commit is contained in:
Linus Torvalds 2022-05-25 14:56:06 -07:00
commit 86c87bea6b
188 changed files with 4364 additions and 1997 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/bcm/brcm,bcm63138.txt
View File

@ -30,7 +30,7 @@ Example:
cpus {
cpu@0 {
compatible = "arm,cotex-a9";
compatible = "arm,cortex-a9";
reg = <0>;
...
enable-method = "brcm,bcm63138";

19
Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
View File

@ -1,19 +0,0 @@
Freescale DCFG
DCFG is the device configuration unit, that provides general purpose
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and startup.
Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
- reg : should contain base address and length of DCFG memory-mapped registers
Example:
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1021a-dcfg";
reg = <0x0 0x1ee0000 0x0 0x10000>;
};

19
Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt
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@ -1,19 +0,0 @@
Freescale SCFG
SCFG is the supplemental configuration unit, that provides SoC specific
configuration and status registers for the chip. Such as getting PEX port
status.
Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-scfg",
The following <chip>s are known to be supported:
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
- reg: should contain base address and length of SCFG memory-mapped registers
Example:
scfg: scfg@1570000 {
compatible = "fsl,ls1021a-scfg";
reg = <0x0 0x1570000 0x0 0x10000>;
};

5
Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml
View File

@ -17,14 +17,15 @@ properties:
- const: hisilicon,hip04-bootwrapper
boot-method:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Address and size of boot method.
[0]: bootwrapper physical address
[1]: bootwrapper size
[2]: relocation physical address
[3]: relocation size
minItems: 1
maxItems: 2
minItems: 2
maxItems: 4
required:
- compatible

35
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
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@ -1,35 +0,0 @@
Mediatek apmixedsys controller
==============================
The Mediatek apmixedsys controller provides the PLLs to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-apmixedsys"
- "mediatek,mt2712-apmixedsys", "syscon"
- "mediatek,mt6765-apmixedsys", "syscon"
- "mediatek,mt6779-apmixedsys", "syscon"
- "mediatek,mt6797-apmixedsys"
- "mediatek,mt7622-apmixedsys"
- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt7986-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8167-apmixedsys", "syscon"
- "mediatek,mt8173-apmixedsys"
- "mediatek,mt8183-apmixedsys", "syscon"
- "mediatek,mt8516-apmixedsys"
- #clock-cells: Must be 1
The apmixedsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt8173-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};

42
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
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@ -1,42 +0,0 @@
Mediatek infracfg controller
============================
The Mediatek infracfg controller provides various clocks and reset
outputs to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt2712-infracfg", "syscon"
- "mediatek,mt6765-infracfg", "syscon"
- "mediatek,mt6779-infracfg_ao", "syscon"
- "mediatek,mt6797-infracfg", "syscon"
- "mediatek,mt7622-infracfg", "syscon"
- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt7986-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8167-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
- "mediatek,mt8183-infracfg", "syscon"
- "mediatek,mt8516-infracfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The infracfg controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Also it uses the common reset controller binding from
Documentation/devicetree/bindings/reset/reset.txt.
The available reset outputs are defined in
dt-bindings/reset/mt*-resets.h
Example:
infracfg: power-controller@10001000 {
compatible = "mediatek,mt8173-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

81
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml Normal file
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@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek Infrastructure System Configuration Controller
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
description:
The Mediatek infracfg controller provides various clocks and reset outputs
to the system. The clock values can be found in <dt-bindings/clock/mt*-clk.h>,
and reset values in <dt-bindings/reset/mt*-reset.h> and
<dt-bindings/reset/mt*-resets.h>.
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2701-infracfg
- mediatek,mt2712-infracfg
- mediatek,mt6765-infracfg
- mediatek,mt6779-infracfg_ao
- mediatek,mt6797-infracfg
- mediatek,mt7622-infracfg
- mediatek,mt7629-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8167-infracfg
- mediatek,mt8173-infracfg
- mediatek,mt8183-infracfg
- mediatek,mt8516-infracfg
- const: syscon
- items:
- const: mediatek,mt7623-infracfg
- const: mediatek,mt2701-infracfg
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-infracfg
- mediatek,mt2712-infracfg
- mediatek,mt7622-infracfg
- mediatek,mt7986-infracfg
- mediatek,mt8135-infracfg
- mediatek,mt8173-infracfg
- mediatek,mt8183-infracfg
then:
required:
- '#reset-cells'
additionalProperties: false
examples:
- |
infracfg: clock-controller@10001000 {
compatible = "mediatek,mt8173-infracfg", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

35
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
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@ -1,35 +0,0 @@
Mediatek topckgen controller
============================
The Mediatek topckgen controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-topckgen"
- "mediatek,mt2712-topckgen", "syscon"
- "mediatek,mt6765-topckgen", "syscon"
- "mediatek,mt6779-topckgen", "syscon"
- "mediatek,mt6797-topckgen"
- "mediatek,mt7622-topckgen"
- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
- "mediatek,mt7629-topckgen"
- "mediatek,mt7986-topckgen", "syscon"
- "mediatek,mt8135-topckgen"
- "mediatek,mt8167-topckgen", "syscon"
- "mediatek,mt8173-topckgen"
- "mediatek,mt8183-topckgen", "syscon"
- "mediatek,mt8516-topckgen"
- #clock-cells: Must be 1
The topckgen controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
topckgen: power-controller@10000000 {
compatible = "mediatek,mt8173-topckgen";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};

46
Documentation/devicetree/bindings/arm/sp810.txt
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@ -1,46 +0,0 @@
SP810 System Controller
-----------------------
Required properties:
- compatible: standard compatible string for a Primecell peripheral,
see Documentation/devicetree/bindings/arm/primecell.yaml
for more details
should be: "arm,sp810", "arm,primecell"
- reg: standard registers property, physical address and size
of the control registers
- clock-names: from the common clock bindings, for more details see
Documentation/devicetree/bindings/clock/clock-bindings.txt;
should be: "refclk", "timclk", "apb_pclk"
- clocks: from the common clock bindings, phandle and clock
specifier pairs for the entries of clock-names property
- #clock-cells: from the common clock bindings;
should be: <1>
- clock-output-names: from the common clock bindings;
should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
- assigned-clocks: from the common clock binding;
should be: clock specifier for each output clock of this
provider node
- assigned-clock-parents: from the common clock binding;
should be: phandle of input clock listed in clocks
property with the highest frequency
Example:
v2m_sysctl: sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};

80
Documentation/devicetree/bindings/arm/sp810.yaml Normal file
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@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sp810.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express SP810 System Controller bindings
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm SP810 system controller provides clocks, timers and a watchdog.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
const: arm,sp810
required:
- compatible
properties:
compatible:
items:
- const: arm,sp810
- const: arm,primecell
reg:
maxItems: 1
clock-names:
items:
- const: refclk
- const: timclk
- const: apb_pclk
clocks:
items:
- description: reference clock
- description: timer clock
- description: APB register access clock
"#clock-cells":
const: 1
clock-output-names:
maxItems: 4
assigned-clocks:
maxItems: 4
assigned-clock-parents:
maxItems: 4
additionalProperties: false
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
examples:
- |
sysctl@20000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclken0", "timerclken1",
"timerclken2", "timerclken3";
assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>,
<&v2m_sysctl 3>, <&v2m_sysctl 3>;
assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>,
<&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
};

20
Documentation/devicetree/bindings/arm/spe-pmu.txt
View File

@ -1,20 +0,0 @@
* ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
performance sample data using an in-memory trace buffer.
** SPE Required properties:
- compatible : should be one of:
"arm,statistical-profiling-extension-v1"
- interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
SPE is only supported on a subset of the CPUs, please consult
the arm,gic-v3 binding for details on describing a PPI partition.
** Example:
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 05 IRQ_TYPE_LEVEL_HIGH &part1>;
};

285
Documentation/devicetree/bindings/arm/vexpress-config.yaml Normal file
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@ -0,0 +1,285 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express configuration bus bindings
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
This is a system control register block, acting as a bridge to the
platform's configuration bus via "system control" interface, addressing
devices with site number, position in the board stack, config controller,
function and device numbers - see motherboard's TRM for more details.
properties:
compatible:
const: arm,vexpress,config-bus
arm,vexpress,config-bridge:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the sysreg node.
muxfpga:
type: object
properties:
compatible:
const: arm,vexpress-muxfpga
arm,vexpress-sysreg,func:
description: FPGA specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 7
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
shutdown:
type: object
properties:
compatible:
const: arm,vexpress-shutdown
arm,vexpress-sysreg,func:
description: shutdown identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 8
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
reboot:
type: object
properties:
compatible:
const: arm,vexpress-reboot
arm,vexpress-sysreg,func:
description: reboot identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 9
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
dvimode:
type: object
properties:
compatible:
const: arm,vexpress-dvimode
arm,vexpress-sysreg,func:
description: DVI mode identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 11
- description: device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
additionalProperties: false
required:
- compatible
- arm,vexpress,config-bridge
patternProperties:
'clk[0-9]*$':
type: object
description:
clocks
properties:
compatible:
const: arm,vexpress-osc
arm,vexpress-sysreg,func:
description: clock specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 1
- description: clock number
freq-range:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: minimal clock frequency
- description: maximum clock frequency
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
- "#clock-cells"
"^volt-.+$":
$ref: /schemas/regulator/regulator.yaml#
properties:
compatible:
const: arm,vexpress-volt
arm,vexpress-sysreg,func:
description: regulator specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 2
- description: device number
label:
maxItems: 1
unevaluatedProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^amp-.+$":
type: object
properties:
compatible:
const: arm,vexpress-amp
arm,vexpress-sysreg,func:
description: current sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 3
- description: device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^temp-.+$":
type: object
properties:
compatible:
const: arm,vexpress-temp
arm,vexpress-sysreg,func:
description: temperature sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 4
- description: device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^reset[0-9]*$":
type: object
properties:
compatible:
const: arm,vexpress-reset
arm,vexpress-sysreg,func:
description: reset specifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 5
- description: reset device number
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^power-.+$":
type: object
properties:
compatible:
const: arm,vexpress-power
arm,vexpress-sysreg,func:
description: power sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- const: 12
- description: device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
"^energy(-.+)?$":
type: object
properties:
compatible:
const: arm,vexpress-energy
arm,vexpress-sysreg,func:
description: energy sensor identifier
$ref: /schemas/types.yaml#/definitions/uint32-array
oneOf:
- items:
- const: 13
- description: device number
- items:
- const: 13
- description: device number
- const: 13
- description: second device number
label:
maxItems: 1
additionalProperties: false
required:
- compatible
- arm,vexpress-sysreg,func
examples:
- |
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
clk0 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
#clock-cells = <0>;
};
energy {
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>, <13 1>;
};
};

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ARM Versatile Express system registers
--------------------------------------
This is a system control registers block, providing multiple low level
platform functions like board detection and identification, software
interrupt generation, MMC and NOR Flash control etc.
Required node properties:
- compatible value : = "arm,vexpress,sysreg";
- reg : physical base address and the size of the registers window
Deprecated properties, replaced by GPIO subnodes (see below):
- gpio-controller : specifies that the node is a GPIO controller
- #gpio-cells : size of the GPIO specifier, should be 2:
- first cell is the pseudo-GPIO line number:
0 - MMC CARDIN
1 - MMC WPROT
2 - NOR FLASH WPn
- second cell can take standard GPIO flags (currently ignored).
Control registers providing pseudo-GPIO lines must be represented
by subnodes, each of them requiring the following properties:
- compatible value : one of
"arm,vexpress-sysreg,sys_led"
"arm,vexpress-sysreg,sys_mci"
"arm,vexpress-sysreg,sys_flash"
- gpio-controller : makes the node a GPIO controller
- #gpio-cells : size of the GPIO specifier, must be 2:
- first cell is the function number:
- for sys_led : 0..7 = LED 0..7
- for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
- for sys_flash : 0 = NOR FLASH WPn
- second cell can take standard GPIO flags (currently ignored).
Example:
v2m_sysreg: sysreg@10000000 {
compatible = "arm,vexpress-sysreg";
reg = <0x10000000 0x1000>;
v2m_led_gpios: sys_led@8 {
compatible = "arm,vexpress-sysreg,sys_led";
gpio-controller;
#gpio-cells = <2>;
};
v2m_mmc_gpios: sys_mci@48 {
compatible = "arm,vexpress-sysreg,sys_mci";
gpio-controller;
#gpio-cells = <2>;
};
v2m_flash_gpios: sys_flash@4c {
compatible = "arm,vexpress-sysreg,sys_flash";
gpio-controller;
#gpio-cells = <2>;
};
};
This block also can also act a bridge to the platform's configuration
bus via "system control" interface, addressing devices with site number,
position in the board stack, config controller, function and device
numbers - see motherboard's TRM for more details. All configuration
controller accessible via this interface must reference the sysreg
node via "arm,vexpress,config-bridge" phandle and define appropriate
topology properties - see main vexpress node documentation for more
details. Each child of such node describes one function and must
define the following properties:
- compatible value : must be one of (corresponding to the TRM):
"arm,vexpress-amp"
"arm,vexpress-dvimode"
"arm,vexpress-energy"
"arm,vexpress-muxfpga"
"arm,vexpress-osc"
"arm,vexpress-power"
"arm,vexpress-reboot"
"arm,vexpress-reset"
"arm,vexpress-scc"
"arm,vexpress-shutdown"
"arm,vexpress-temp"
"arm,vexpress-volt"
- arm,vexpress-sysreg,func : must contain a set of two cells long groups:
- first cell of each group defines the function number
(eg. 1 for clock generator, 2 for voltage regulators etc.)
- second cell of each group defines device number (eg. osc 0,
osc 1 etc.)
- some functions (eg. energy meter, with its 64 bit long counter)
are using more than one function/device number pair
Example:
mcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
osc@0 {
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
};
energy@0 {
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>, <13 1>;
};
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express system registers bindings
maintainers:
- Andre Przywara <andre.przywara@arm.com>
description:
This is a system control registers block, providing multiple low level
platform functions like board detection and identification, software
interrupt generation, MMC and NOR Flash control, etc.
properties:
compatible:
const: arm,vexpress-sysreg
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
additionalProperties: false
patternProperties:
'^gpio@[0-9a-f]+$':
type: object
additionalProperties: false
description:
GPIO children
properties:
compatible:
enum:
- arm,vexpress-sysreg,sys_led
- arm,vexpress-sysreg,sys_mci
- arm,vexpress-sysreg,sys_flash
gpio-controller: true
"#gpio-cells":
const: 2
description: |
The first cell is the function number:
for sys_led : 0..7 = LED 0..7
for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
for sys_flash : 0 = NOR FLASH WPn
The second cell can take standard GPIO flags.
reg:
maxItems: 1
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
required:
- compatible
- "#address-cells"
- "#size-cells"
examples:
- |
sysreg@0 {
compatible = "arm,vexpress-sysreg";
reg = <0x00000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000>;
v2m_led_gpios: gpio@8 {
compatible = "arm,vexpress-sysreg,sys_led";
reg = <0x008 4>;
gpio-controller;
#gpio-cells = <2>;
};
};
...

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek AP Mixedsys Controller
maintainers:
- Michael Turquette <mturquette@baylibre.com>
- Stephen Boyd <sboyd@kernel.org>
description:
The Mediatek apmixedsys controller provides PLLs to the system.
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6797-apmixedsys
- mediatek,mt7622-apmixedsys
- mediatek,mt7986-apmixedsys
- mediatek,mt8135-apmixedsys
- mediatek,mt8173-apmixedsys
- mediatek,mt8516-apmixedsys
- items:
- const: mediatek,mt7623-apmixedsys
- const: mediatek,mt2701-apmixedsys
- const: syscon
- items:
- enum:
- mediatek,mt2701-apmixedsys
- mediatek,mt2712-apmixedsys
- mediatek,mt6765-apmixedsys
- mediatek,mt6779-apmixedsys
- mediatek,mt7629-apmixedsys
- mediatek,mt8167-apmixedsys
- mediatek,mt8183-apmixedsys
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt8173-apmixedsys";
reg = <0x10209000 0x1000>;
#clock-cells = <1>;
};

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MediaTek Top Clock Generator Controller
maintainers:
- Michael Turquette <mturquette@baylibre.com>
- Stephen Boyd <sboyd@kernel.org>
description:
The Mediatek topckgen controller provides various clocks to the system.
The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt6797-topckgen
- mediatek,mt7622-topckgen
- mediatek,mt8135-topckgen
- mediatek,mt8173-topckgen
- mediatek,mt8516-topckgen
- items:
- const: mediatek,mt7623-topckgen
- const: mediatek,mt2701-topckgen
- const: syscon
- items:
- enum:
- mediatek,mt2701-topckgen
- mediatek,mt2712-topckgen
- mediatek,mt6765-topckgen
- mediatek,mt6779-topckgen
- mediatek,mt7629-topckgen
- mediatek,mt7986-topckgen
- mediatek,mt8167-topckgen
- mediatek,mt8183-topckgen
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
topckgen: clock-controller@10000000 {
compatible = "mediatek,mt8173-topckgen";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
};

1
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@ -61,4 +61,3 @@ examples:
clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
clock-names = "aclk200", "aclk400_mcuisp";
};

1
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@ -82,4 +82,3 @@ examples:
clock-names = "bus", "mod";
resets = <&ccu RST_BUS_CE>;
};

1
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@ -150,4 +150,3 @@ examples:
};
};
};

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ARM HDLCD
This is a display controller found on several development platforms produced
by ARM Ltd and in more modern of its' Fast Models. The HDLCD is an RGB
streamer that reads the data from a framebuffer and sends it to a single
digital encoder (DVI or HDMI).
Required properties:
- compatible: "arm,hdlcd"
- reg: Physical base address and length of the controller's registers.
- interrupts: One interrupt used by the display controller to notify the
interrupt controller when any of the interrupt sources programmed in
the interrupt mask register have activated.
- clocks: A list of phandle + clock-specifier pairs, one for each
entry in 'clock-names'.
- clock-names: A list of clock names. For HDLCD it should contain:
- "pxlclk" for the clock feeding the output PLL of the controller.
Required sub-nodes:
- port: The HDLCD connection to an encoder chip. The connection is modeled
using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt.
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be
used for the framebuffer; if not present, the framebuffer may be located
anywhere in memory.
Example:
/ {
...
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0 0x2b000000 0 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
port {
hdlcd_output: endpoint@0 {
remote-endpoint = <&hdmi_enc_input>;
};
};
};
/* HDMI encoder on I2C bus */
i2c@7ffa0000 {
....
hdmi-transmitter@70 {
compatible = ".....";
reg = <0x70>;
port@0 {
hdmi_enc_input: endpoint {
remote-endpoint = <&hdlcd_output>;
};
hdmi_enc_output: endpoint {
remote-endpoint = <&hdmi_1_port>;
};
};
};
};
hdmi1: connector@1 {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_1_port: endpoint {
remote-endpoint = <&hdmi_enc_output>;
};
};
};
...
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,hdlcd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm HDLCD display controller binding
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm HDLCD is a display controller found on several development platforms
produced by ARM Ltd and in more modern of its Fast Models. The HDLCD is an
RGB streamer that reads the data from a framebuffer and sends it to a single
digital encoder (DVI or HDMI).
properties:
compatible:
const: arm,hdlcd
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
const: pxlclk
clocks:
maxItems: 1
description: The input reference for the pixel clock.
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
iommus:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- port
examples:
- |
hdlcd@2b000000 {
compatible = "arm,hdlcd";
reg = <0x2b000000 0x1000>;
interrupts = <0 85 4>;
clocks = <&oscclk5>;
clock-names = "pxlclk";
port {
hdlcd_output: endpoint {
remote-endpoint = <&hdmi_enc_input>;
};
};
};
/* HDMI encoder on I2C bus */
i2c {
#address-cells = <1>;
#size-cells = <0>;
hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
port {
hdmi_enc_input: endpoint {
remote-endpoint = <&hdlcd_output>;
};
};
};
};
...

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Device Tree bindings for Arm Komeda display driver
Required properties:
- compatible: Should be "arm,mali-d71"
- reg: Physical base address and length of the registers in the system
- interrupts: the interrupt line number of the device in the system
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "aclk": for the main processor clock
- #address-cells: Must be 1
- #size-cells: Must be 0
- iommus: configure the stream id to IOMMU, Must be configured if want to
enable iommu in display. for how to configure this node please reference
devicetree/bindings/iommu/arm,smmu-v3.txt,
devicetree/bindings/iommu/iommu.txt
Required properties for sub-node: pipeline@nq
Each device contains one or two pipeline sub-nodes (at least one), each
pipeline node should provide properties:
- reg: Zero-indexed identifier for the pipeline
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: should contain:
- "pxclk": pixel clock
- port: each pipeline connect to an encoder input port. The connection is
modeled using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer may
be located anywhere in memory.
Example:
/ {
...
dp0: display@c00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <0xc00000 0x20000>;
interrupts = <0 168 4>;
clocks = <&dpu_aclk>;
clock-names = "aclk";
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
<&smmu 8>, <&smmu 9>;
dp0_pipe0: pipeline@0 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <0>;
port {
dp0_pipe0_out: endpoint {
remote-endpoint = <&db_dvi0_in>;
};
};
};
dp0_pipe1: pipeline@1 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <1>;
port {
dp0_pipe1_out: endpoint {
remote-endpoint = <&db_dvi1_in>;
};
};
};
};
...
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,komeda.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Komeda display processor
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm Mali D71 display processor supports up to two displays with up
to a 4K resolution each. Each pipeline can be composed of up to four
layers. It is typically connected to a digital display connector like HDMI.
properties:
compatible:
oneOf:
- items:
- const: arm,mali-d32
- const: arm,mali-d71
- const: arm,mali-d71
reg:
maxItems: 1
interrupts:
maxItems: 1
clock-names:
const: aclk
clocks:
maxItems: 1
description: The main DPU processor clock
"#address-cells":
const: 1
"#size-cells":
const: 0
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
iommus:
description:
The stream IDs for each of the used pipelines, each four IDs for the
four layers, plus one for the write-back stream.
minItems: 5
maxItems: 10
patternProperties:
'^pipeline@[01]$':
type: object
description:
clocks
properties:
reg:
enum: [ 0, 1 ]
clock-names:
const: pxclk
clocks:
maxItems: 1
description: The input reference for the pixel clock.
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
additionalProperties: false
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
- interrupts
- clock-names
- clocks
- pipeline@0
examples:
- |
display@c00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,mali-d71";
reg = <0xc00000 0x20000>;
interrupts = <168>;
clocks = <&dpu_aclk>;
clock-names = "aclk";
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
<&smmu 8>,
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
<&smmu 9>;
dp0_pipe0: pipeline@0 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <0>;
port {
dp0_pipe0_out: endpoint {
remote-endpoint = <&db_dvi0_in>;
};
};
};
dp0_pipe1: pipeline@1 {
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <1>;
port {
dp0_pipe1_out: endpoint {
remote-endpoint = <&db_dvi1_in>;
};
};
};
};
...

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ARM Mali-DP
The following bindings apply to a family of Display Processors sold as
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
DP650 processors that offer multiple composition layers, support for
rotation and scaling output.
Required properties:
- compatible: should be one of
"arm,mali-dp500"
"arm,mali-dp550"
"arm,mali-dp650"
depending on the particular implementation present in the hardware
- reg: Physical base address and size of the block of registers used by
the processor.
- interrupts: Interrupt list, as defined in ../interrupt-controller/interrupts.txt,
interrupt client nodes.
- interrupt-names: name of the engine inside the processor that will
use the corresponding interrupt. Should be one of "DE" or "SE".
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "pclk": for the APB interface clock
- "aclk": for the AXI interface clock
- "mclk": for the main processor clock
- "pxlclk": for the pixel clock feeding the output PLL of the processor.
- arm,malidp-output-port-lines: Array of u8 values describing the number
of output lines per channel (R, G and B).
Required sub-nodes:
- port: The Mali DP connection to an encoder input port. The connection
is modelled using the OF graph bindings specified in
Documentation/devicetree/bindings/graph.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer may
be located anywhere in memory.
- arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS
levels of DP500's QoS signaling.
Example:
/ {
...
dp0: malidp@6f200000 {
compatible = "arm,mali-dp650";
reg = <0 0x6f200000 0 0x20000>;
memory-region = <&display_reserved>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>,
<0 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-high-level = <0xd000d000>;
port {
dp0_output: endpoint {
remote-endpoint = <&tda998x_2_input>;
};
};
};
...
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,malidp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Mali Display Processor (Mali-DP) binding
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The following bindings apply to a family of Display Processors sold as
licensable IP by ARM Ltd. The bindings describe the Mali DP500, DP550 and
DP650 processors that offer multiple composition layers, support for
rotation and scaling output.
properties:
compatible:
enum:
- arm,mali-dp500
- arm,mali-dp550
- arm,mali-dp650
reg:
maxItems: 1
interrupts:
items:
- description:
The interrupt used by the Display Engine (DE). Can be shared with
the interrupt for the Scaling Engine (SE), but it will have to be
listed individually.
- description:
The interrupt used by the Scaling Engine (SE). Can be shared with
the interrupt for the Display Engine (DE), but it will have to be
listed individually.
interrupt-names:
items:
- const: DE
- const: SE
clock-names:
items:
- const: pxlclk
- const: mclk
- const: aclk
- const: pclk
clocks:
items:
- description: the pixel clock feeding the output PLL of the processor
- description: the main processor clock
- description: the AXI interface clock
- description: the APB interface clock
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
arm,malidp-output-port-lines:
$ref: /schemas/types.yaml#/definitions/uint8-array
description:
Number of output lines/bits for each colour channel.
items:
- description: number of output lines for the red channel (R)
- description: number of output lines for the green channel (G)
- description: number of output lines for the blue channel (B)
arm,malidp-arqos-high-level:
$ref: /schemas/types.yaml#/definitions/uint32
description:
integer describing the ARQoS levels of DP500's QoS signaling
arm,malidp-arqos-value:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Quality-of-Service value for the display engine FIFOs, to write
into the RQOS register of the DP500.
See the ARM Mali-DP500 TRM for details on the encoding.
If omitted, the RQOS register will not be changed.
port:
$ref: /schemas/graph.yaml#/properties/port
unevaluatedProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- port
- arm,malidp-output-port-lines
examples:
- |
dp0: malidp@6f200000 {
compatible = "arm,mali-dp650";
reg = <0x6f200000 0x20000>;
memory-region = <&display_reserved>;
interrupts = <168>, <168>;
interrupt-names = "DE", "SE";
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-high-level = <0xd000d000>;
port {
dp0_output: endpoint {
remote-endpoint = <&tda998x_2_input>;
};
};
};
...

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@ -1,110 +0,0 @@
* ARM PrimeCell Color LCD Controller PL110/PL111
See also Documentation/devicetree/bindings/arm/primecell.yaml
Required properties:
- compatible: must be one of:
"arm,pl110", "arm,primecell"
"arm,pl111", "arm,primecell"
- reg: base address and size of the control registers block
- interrupt-names: either the single entry "combined" representing a
combined interrupt output (CLCDINTR), or the four entries
"mbe", "vcomp", "lnbu", "fuf" representing the individual
CLCDMBEINTR, CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR interrupts
- interrupts: contains an interrupt specifier for each entry in
interrupt-names
- clock-names: should contain "clcdclk" and "apb_pclk"
- clocks: contains phandle and clock specifier pairs for the entries
in the clock-names property. See
Documentation/devicetree/bindings/clock/clock-bindings.txt
Optional properties:
- memory-region: phandle to a node describing memory (see
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer
may be located anywhere in the memory
- max-memory-bandwidth: maximum bandwidth in bytes per second that the
cell's memory interface can handle; if not present, the memory
interface is fast enough to handle all possible video modes
Required sub-nodes:
- port: describes LCD panel signals, following the common binding
for video transmitter interfaces; see
Documentation/devicetree/bindings/media/video-interfaces.txt
Deprecated properties:
The port's endbpoint subnode had this, now deprecated property
in the past. Drivers should be able to survive without it:
- arm,pl11x,tft-r0g0b0-pads: an array of three 32-bit values,
defining the way CLD pads are wired up; first value
contains index of the "CLD" external pin (pad) used
as R0 (first bit of the red component), second value
index of the pad used as G0, third value index of the
pad used as B0, see also "LCD panel signal multiplexing
details" paragraphs in the PL110/PL111 Technical
Reference Manuals; this implicitly defines available
color modes, for example:
- PL111 TFT 4:4:4 panel:
arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
- PL110 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
- PL111 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
- PL111 TFT 5:6:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
- PL110 and PL111 TFT 8:8:8 panel:
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
Example:
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-names = "combined";
interrupts = <0 44 4>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
};
};
};
panel {
compatible = "panel-dpi";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};

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@ -0,0 +1,183 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/arm,pl11x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm PrimeCell Color LCD Controller PL110/PL111
maintainers:
- Liviu Dudau <Liviu.Dudau@arm.com>
- Andre Przywara <andre.przywara@arm.com>
description:
The Arm Primcell PL010/PL111 is an LCD controller IP, than scans out
a framebuffer region in system memory, and creates timed signals for
a variety of LCD panels.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,pl110
- arm,pl111
required:
- compatible
properties:
compatible:
items:
- enum:
- arm,pl110
- arm,pl111
- const: arm,primecell
reg:
maxItems: 1
interrupt-names:
oneOf:
- const: combined
description:
The IP provides four individual interrupt lines, but also one
combined line. If the integration only connects this line to the
interrupt controller, this single interrupt is noted here.
- items:
- const: mbe # CLCDMBEINTR
- const: vcomp # CLCDVCOMPINTR
- const: lnbu # CLCDLNBUINTR
- const: fuf # CLCDFUFINTR
interrupts:
minItems: 1
maxItems: 4
clock-names:
items:
- const: clcdclk
- const: apb_pclk
clocks:
items:
- description: The CLCDCLK reference clock for the controller.
- description: The HCLK AHB slave clock for the register access.
memory-region:
maxItems: 1
description:
Phandle to a node describing memory to be used for the framebuffer.
If not present, the framebuffer may be located anywhere in memory.
max-memory-bandwidth:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Maximum bandwidth in bytes per second that the cell's memory interface
can handle.
If not present, the memory interface is fast enough to handle all
possible video modes.
port:
$ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
description:
Output endpoint of the controller, connecting the LCD panel signals.
properties:
endpoint:
$ref: /schemas/graph.yaml#/$defs/endpoint-base
unevaluatedProperties: false
properties:
arm,pl11x,tft-r0g0b0-pads:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: index of CLD pad used for first red bit (R0)
- description: index of CLD pad used for first green bit (G0)
- description: index of CLD pad used for first blue bit (G0)
deprecated: true
description: |
DEPRECATED. An array of three 32-bit values, defining the way
CLD[23:0] pads are wired up.
The first value contains the index of the "CLD" external pin (pad)
used as R0 (first bit of the red component), the second value for
green, the third value for blue.
See also "LCD panel signal multiplexing details" paragraphs in the
PL110/PL111 Technical Reference Manuals.
This implicitly defines available color modes, for example:
- PL111 TFT 4:4:4 panel:
arm,pl11x,tft-r0g0b0-pads = <4 15 20>;
- PL110 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <1 7 13>;
- PL111 TFT (1:)5:5:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 11 19>;
- PL111 TFT 5:6:5 panel:
arm,pl11x,tft-r0g0b0-pads = <3 10 19>;
- PL110 and PL111 TFT 8:8:8 panel:
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- PL110 and PL111 TFT 8:8:8 panel, R & B components swapped:
arm,pl11x,tft-r0g0b0-pads = <16 8 0>;
additionalProperties: false
required:
- compatible
- reg
- clock-names
- clocks
- port
allOf:
- if:
properties:
interrupts:
minItems: 2
required:
- interrupts
then:
required:
- interrupt-names
examples:
- |
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-names = "combined";
interrupts = <44>;
clocks = <&oscclk1>, <&oscclk2>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <94371840>; /* Bps, 1024x768@60 16bpp */
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
};
};
};
panel {
compatible = "arm,rtsm-display", "panel-dpi";
power-supply = <&vcc_supply>;
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <25175000>;
hactive = <640>;
hback-porch = <40>;
hfront-porch = <24>;
hsync-len = <96>;
vactive = <480>;
vback-porch = <32>;
vfront-porch = <11>;
vsync-len = <2>;
};
};
...

1
Documentation/devicetree/bindings/display/bridge/google,cros-ec-anx7688.yaml
View File

@ -78,4 +78,3 @@ examples:
};
};
};

1
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@ -119,4 +119,3 @@ examples:
};
};
};

1
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View File

@ -58,6 +58,7 @@ properties:
properties:
data-lines:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 16, 18, 24 ]
port@1:

1
Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
View File

@ -105,4 +105,3 @@ examples:
};
};
};

1
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
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@ -102,4 +102,3 @@ examples:
clock-names = "merge";
};
};

1
Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
View File

@ -75,4 +75,3 @@ examples:
};
};
...

1
Documentation/devicetree/bindings/display/panel/orisetech,otm8009a.yaml
View File

@ -50,4 +50,3 @@ examples:
};
};
...

5
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@ -146,6 +146,7 @@ properties:
Horizontal sync pulse.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
vsync-active:
@ -153,6 +154,7 @@ properties:
Vertical sync pulse.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
de-active:
@ -160,6 +162,7 @@ properties:
Data enable.
0 selects active low, 1 selects active high.
If omitted then it is not used by the hardware
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
pixelclk-active:
@ -169,6 +172,7 @@ properties:
sample data on rising edge.
Use 1 to drive pixel data on rising edge and
sample data on falling edge
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
syncclk-active:
@ -179,6 +183,7 @@ properties:
sample sync on rising edge of pixel clock.
Use 1 to drive sync on rising edge and
sample sync on falling edge of pixel clock
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
interlaced:

1
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View File

@ -24,6 +24,7 @@ properties:
dsi-lanes:
description: Number of DSI lanes to be used must be <3> or <4>
$ref: /schemas/types.yaml#/definitions/uint32
enum: [3, 4]
v3p3-supply:

1
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View File

@ -36,6 +36,7 @@ properties:
init-delay:
description: delay after initialization sequence [ms]
$ref: /schemas/types.yaml#/definitions/uint32
panel-width-mm:
description: physical panel width [mm]

1
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View File

@ -63,4 +63,3 @@ examples:
compatible = "sprd,display-subsystem";
ports = <&dpu_out>;
};

1
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@ -75,4 +75,3 @@ examples:
};
...

1
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@ -51,4 +51,3 @@ examples:
};
...

1
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@ -104,4 +104,3 @@ examples:
};
...

1
Documentation/devicetree/bindings/eeprom/at24.txt
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@ -1 +0,0 @@
This file has been moved to at24.yaml.

4
Documentation/devicetree/bindings/eeprom/at24.yaml
View File

@ -120,7 +120,9 @@ properties:
- const: giantec,gt24c32a
- const: atmel,24c32
- items:
- const: renesas,r1ex24128
- enum:
- renesas,r1ex24128
- samsung,s524ad0xd1
- const: atmel,24c128
label:

14
Documentation/devicetree/bindings/example-schema.yaml
View File

@ -249,13 +249,13 @@ examples:
# be overridden or an appropriate parent bus node should be shown (such as on
# i2c buses).
#
# Any includes used have to be explicitly included.
# Any includes used have to be explicitly included. Use 4-space indentation.
- |
node@1000 {
compatible = "vendor,soc4-ip", "vendor,soc1-ip";
reg = <0x1000 0x80>,
<0x3000 0x80>;
reg-names = "core", "aux";
interrupts = <10>;
interrupt-controller;
compatible = "vendor,soc4-ip", "vendor,soc1-ip";
reg = <0x1000 0x80>,
<0x3000 0x80>;
reg-names = "core", "aux";
interrupts = <10>;
interrupt-controller;
};

69
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@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/brcm,bcm4751.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4751 family GNSS Receiver Device Tree Bindings
maintainers:
- Johan Hovold <johan@kernel.org>
- Linus Walleij <linus.walleij@linaro.org>
description:
Broadcom GPS chips can be used over the UART or I2C bus. The UART
bus requires CTS/RTS support. The number of the capsule is more
elaborate than the compatibles BCM4751 may be printed
BCM4751IFBG for example.
allOf:
- $ref: gnss-common.yaml#
properties:
compatible:
enum:
- brcm,bcm4751
- brcm,bcm4752
- brcm,bcm4753
reg:
description:
The I2C Address, not required on UART buses.
vdd-auxin-supply:
description:
Main voltage supply, pin name VDD_AUXIN, typically connected
directly to a battery such as LiIon 3.8V battery or a 2.6V supply.
vddio-supply:
description:
IO voltage supply, pin name VDDIO, typically 1.8V
reset-gpios:
maxItems: 1
description: An optional active low reset line, should be flagged with
GPIO_ACTIVE_LOW.
enable-gpios:
description: Enable GPIO line, connected to pins named REGPU or NSTANDBY.
If the line is active low such as NSTANDBY, it should be tagged
GPIO_ACTIVE_LOW.
required:
- compatible
- enable-gpios
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
serial {
gnss {
compatible = "brcm,bcm4751";
vdd-auxin-supply = <&vbat>;
reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
current-speed = <38400>;
};
};

35
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@ -1,35 +0,0 @@
Mediatek-based GNSS Receiver DT binding
Mediatek chipsets are used in GNSS-receiver modules produced by several
vendors and can use a UART interface.
Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
properties.
Required properties:
- compatible : Must be
"globaltop,pa6h"
- vcc-supply : Main voltage regulator (pin name: VCC)
Optional properties:
- current-speed : Default UART baud rate
- gnss-fix-gpios : GPIO used to determine device position fix state
(pin name: FIX, 3D_FIX)
- reset-gpios : GPIO used to reset the device (pin name: RESET, NRESET)
- timepulse-gpios : Time pulse GPIO (pin name: PPS1, 1PPS)
- vbackup-supply : Backup voltage regulator (pin name: VBAT, VBACKUP)
Example:
serial@1234 {
compatible = "ns16550a";
gnss {
compatible = "globaltop,pa6h";
vcc-supply = <&vcc_3v3>;
};
};

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@ -0,0 +1,59 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/mediatek.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek GNSS Receiver Device Tree Bindings
maintainers:
- Johan Hovold <johan@kernel.org>
description:
Mediatek chipsets are used in GNSS-receiver modules produced by several
vendors and can use a UART interface.
allOf:
- $ref: gnss-common.yaml#
properties:
compatible:
const: globaltop,pa6h
vcc-supply:
description:
Main voltage regulator, pin name VCC.
reset-gpios:
maxItems: 1
description: An optional reset line, with names such as RESET or NRESET.
If the line is active low it should be flagged with GPIO_ACTIVE_LOW.
timepulse-gpios:
description: Comes with pin names such as PPS1 or 1PPS.
gnss-fix-gpios:
maxItems: 1
description: GPIO used to determine device position fix state, pin names
FIX or 3D_FIX.
vbackup-supply:
description:
Regulator providing backup voltage, pin names such as VBAT or VBACKUP.
required:
- compatible
- vcc-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
serial {
gnss {
compatible = "globaltop,pa6h";
vcc-supply = <&vcc_3v3>;
reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
};

1
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@ -26,6 +26,7 @@ properties:
const: 2
registers-number:
$ref: /schemas/types.yaml#/definitions/uint32
description: Number of daisy-chained shift registers
enable-gpios:

1
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@ -53,4 +53,3 @@ examples:
clocks = <&clock 278>;
clock-names = "rotator";
};

1
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@ -103,4 +103,3 @@ examples:
adi,pin14-function = "tach4";
};
};

1
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@ -36,4 +36,3 @@ examples:
};
};
...

53
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@ -1,53 +0,0 @@
* MediaTek's I2C controller
The MediaTek's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
"mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
"mediatek,mt2712-i2c": for MediaTek MT2712
"mediatek,mt6577-i2c": for MediaTek MT6577
"mediatek,mt6589-i2c": for MediaTek MT6589
"mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797
"mediatek,mt7622-i2c": for MediaTek MT7622
"mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
"mediatek,mt8168-i2c": for MediaTek MT8168
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
"mediatek,mt8186-i2c": for MediaTek MT8186
"mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
- interrupts: interrupt number to the cpu.
- clock-div: the fixed value for frequency divider of clock source in i2c
module. Each IC may be different.
- clocks: clock name from clock manager
- clock-names: Must include "main" and "dma", "arb" is for multi-master that
one bus has more than two i2c controllers, if enable have-pmic need include
"pmic" extra.
Optional properties:
- clock-frequency: Frequency in Hz of the bus when transfer, the default value
is 100000.
- mediatek,have-pmic: platform can control i2c form special pmic side.
Only mt6589 and mt8135 support this feature.
- mediatek,use-push-pull: IO config use push-pull mode.
- vbus-supply: phandle to the regulator that provides power to SCL/SDA.
Example:
i2c0: i2c@1100d000 {
compatible = "mediatek,mt6577-i2c";
reg = <0x1100d000 0x70>,
<0x11000300 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <400000>;
mediatek,have-pmic;
clock-div = <16>;
clocks = <&i2c0_ck>, <&ap_dma_ck>;
clock-names = "main", "dma";
};

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@ -0,0 +1,118 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-mt65xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek I2C controller
description:
This driver interfaces with the native I2C controller present in
various MediaTek SoCs.
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
maintainers:
- Qii Wang <qii.wang@mediatek.com>
properties:
compatible:
oneOf:
- const: mediatek,mt2712-i2c
- const: mediatek,mt6577-i2c
- const: mediatek,mt6589-i2c
- const: mediatek,mt7622-i2c
- const: mediatek,mt8168-i2c
- const: mediatek,mt8173-i2c
- const: mediatek,mt8183-i2c
- const: mediatek,mt8186-i2c
- const: mediatek,mt8192-i2c
- items:
- enum:
- mediatek,mt7629-i2c
- mediatek,mt8516-i2c
- const: mediatek,mt2712-i2c
- items:
- enum:
- mediatek,mt2701-i2c
- mediatek,mt6797-i2c
- mediatek,mt7623-i2c
- const: mediatek,mt6577-i2c
- items:
- enum:
- mediatek,mt8195-i2c
- const: mediatek,mt8192-i2c
reg:
items:
- description: Physical base address
- description: DMA base address
interrupts:
maxItems: 1
clocks:
minItems: 2
items:
- description: Main clock for I2C bus
- description: Clock for I2C via DMA
- description: Bus arbitrator clock
- description: Clock for I2C from PMIC
clock-names:
minItems: 2
items:
- const: main
- const: dma
- const: arb
- const: pmic
clock-div:
$ref: /schemas/types.yaml#/definitions/uint32
description: Frequency divider of clock source in I2C module
clock-frequency:
default: 100000
description:
SCL frequency to use (in Hz). If omitted, 100kHz is used.
mediatek,have-pmic:
description: Platform controls I2C from PMIC side
type: boolean
mediatek,use-push-pull:
description: Use push-pull mode I/O config
type: boolean
vbus-supply:
description: Phandle to the regulator providing power to SCL/SDA
required:
- compatible
- reg
- clocks
- clock-names
- clock-div
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c0: i2c@1100d000 {
compatible = "mediatek,mt6577-i2c";
reg = <0x1100d000 0x70>, <0x11000300 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
clocks = <&i2c0_ck>, <&ap_dma_ck>;
clock-names = "main", "dma";
clock-div = <16>;
clock-frequency = <400000>;
mediatek,have-pmic;
#address-cells = <1>;
#size-cells = <0>;
};

1
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@ -28,7 +28,6 @@ description: |+
'------------' '-----' '-----' '-----'
allOf:
- $ref: /schemas/i2c/i2c-mux.yaml#

100
Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml Normal file
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@ -0,0 +1,100 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Geni based QUP I2C Controller
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
const: qcom,geni-i2c
clocks:
maxItems: 1
clock-names:
const: se
clock-frequency:
default: 100000
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interconnects:
maxItems: 3
interconnect-names:
items:
- const: qup-core
- const: qup-config
- const: qup-memory
interrupts:
maxItems: 1
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
power-domains:
maxItems: 1
reg:
maxItems: 1
required-opps:
maxItems: 1
required:
- compatible
- interrupts
- clocks
- clock-names
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/interconnect/qcom,sc7180.h>
#include <dt-bindings/power/qcom-rpmpd.h>
i2c@88000 {
compatible = "qcom,geni-i2c";
reg = <0x00880000 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config", "qup-memory";
power-domains = <&rpmhpd SC7180_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

40
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@ -1,40 +0,0 @@
Qualcomm Universal Peripheral (QUP) I2C controller
Required properties:
- compatible: Should be:
* "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064.
* "qcom,i2c-qup-v2.1.1" for 8974 v1.
* "qcom,i2c-qup-v2.2.1" for 8974 v2 and later.
- reg: Should contain QUP register address and length.
- interrupts: Should contain I2C interrupt.
- clocks: A list of phandles + clock-specifiers, one for each entry in
clock-names.
- clock-names: Should contain:
* "core" for the core clock
* "iface" for the AHB clock
- #address-cells: Should be <1> Address cells for i2c device address
- #size-cells: Should be <0> as i2c addresses have no size component
Optional properties:
- clock-frequency: Should specify the desired i2c bus clock frequency in Hz,
defaults to 100kHz if omitted.
Child nodes should conform to i2c bus binding.
Example:
i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x1000>;
interrupts = <0 96 0>;
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
clock-frequency = <355000>;
#address-cells = <1>;
#size-cells = <0>;
};

89
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@ -0,0 +1,89 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Universal Peripheral (QUP) I2C controller
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <bjorn.andersson@linaro.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
properties:
compatible:
enum:
- qcom,i2c-qup-v1.1.1 # for 8660, 8960 and 8064
- qcom,i2c-qup-v2.1.1 # for 8974 v1
- qcom,i2c-qup-v2.2.1 # for 8974 v2 and later
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: iface
clock-frequency:
default: 100000
dmas:
maxItems: 2
dma-names:
items:
- const: tx
- const: rx
interrupts:
maxItems: 1
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
minItems: 1
items:
- const: default
- const: sleep
reg:
maxItems: 1
required:
- compatible
- clock-names
- clocks
- interrupts
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@c175000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c175000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c1_default>;
pinctrl-1 = <&blsp1_i2c1_sleep>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};

2
Documentation/devicetree/bindings/i2c/renesas,riic.yaml
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@ -19,6 +19,7 @@ properties:
- enum:
- renesas,riic-r7s72100 # RZ/A1H
- renesas,riic-r7s9210 # RZ/A2M
- renesas,riic-r9a07g043 # RZ/G2UL
- renesas,riic-r9a07g044 # RZ/G2{L,LC}
- renesas,riic-r9a07g054 # RZ/V2L
- const: renesas,riic-rz # RZ/A or RZ/G2L
@ -75,6 +76,7 @@ if:
compatible:
contains:
enum:
- renesas,riic-r9a07g043
- renesas,riic-r9a07g044
- renesas,riic-r9a07g054
then:

2
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml
View File

@ -123,7 +123,7 @@ examples:
samsung,i2c-slave-addr = <0x66>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
compatible = "samsung,s524ad0xd1", "atmel,24c128";
reg = <0x50>;
};
};

1
Documentation/devicetree/bindings/iio/adc/adi,ad7291.yaml
View File

@ -44,4 +44,3 @@ examples:
};
};
...

2
Documentation/devicetree/bindings/iio/dac/lltc,ltc1660.yaml
View File

@ -41,7 +41,7 @@ examples:
spi {
#address-cells = <1>;
#size-cells = <0>;
dac@0 {
compatible = "lltc,ltc1660";
reg = <0>;

1
Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml
View File

@ -31,6 +31,7 @@ properties:
type: boolean
function-row-physmap:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 15
description: |

27
Documentation/devicetree/bindings/input/ilitek,ili2xxx.txt
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@ -1,27 +0,0 @@
Ilitek ILI210x/ILI2117/ILI2120/ILI251x touchscreen controller
Required properties:
- compatible:
ilitek,ili210x for ILI210x
ilitek,ili2117 for ILI2117
ilitek,ili2120 for ILI2120
ilitek,ili251x for ILI251x
- reg: The I2C address of the device
- interrupts: The sink for the touchscreen's IRQ output
See ../interrupt-controller/interrupts.txt
Optional properties for main touchpad device:
- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
Example:
touchscreen@41 {
compatible = "ilitek,ili251x";
reg = <0x41>;
interrupt-parent = <&gpio4>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
};

7
Documentation/devicetree/bindings/input/touchscreen/ilitek_ts_i2c.yaml
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@ -15,6 +15,9 @@ allOf:
properties:
compatible:
enum:
- ilitek,ili210x
- ilitek,ili2117
- ilitek,ili2120
- ilitek,ili2130
- ilitek,ili2131
- ilitek,ili2132
@ -22,11 +25,12 @@ properties:
- ilitek,ili2322
- ilitek,ili2323
- ilitek,ili2326
- ilitek,ili251x
- ilitek,ili2520
- ilitek,ili2521
reg:
const: 0x41
maxItems: 1
interrupts:
maxItems: 1
@ -50,7 +54,6 @@ required:
- compatible
- reg
- interrupts
- reset-gpios
examples:
- |

53
Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
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@ -1,53 +0,0 @@
* Freescale Layerscape external IRQs
Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
LS1088A, LS208xA, LX216xA) support inverting
the polarity of certain external interrupt lines.
The device node must be a child of the node representing the
Supplemental Configuration Unit (SCFG).
Required properties:
- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
"fsl,ls1043a-extirq": for LS1043A, LS1046A.
"fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
- #interrupt-cells: Must be 2. The first element is the index of the
external interrupt line. The second element is the trigger type.
- #address-cells: Must be 0.
- interrupt-controller: Identifies the node as an interrupt controller
- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
the SCFG or the External Interrupt Control Register (IRQCR) in
the ISC.
- interrupt-map: Specifies the mapping from external interrupts to GIC
interrupts.
- interrupt-map-mask: Must be <0xffffffff 0>.
Example:
scfg: scfg@1570000 {
compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x1570000 0x10000>;
extirq: interrupt-controller@1ac {
compatible = "fsl,ls1021a-extirq";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1ac 4>;
interrupt-map =
<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
};
};
interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<&extirq 1 IRQ_TYPE_LEVEL_LOW>;

118
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@ -0,0 +1,118 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Layerscape External Interrupt Controller
maintainers:
- Shawn Guo <shawnguo@kernel.org>
- Li Yang <leoyang.li@nxp.com>
description: |
Some Layerscape SOCs (LS1021A, LS1043A, LS1046A LS1088A, LS208xA,
LX216xA) support inverting the polarity of certain external interrupt
lines.
properties:
compatible:
oneOf:
- enum:
- fsl,ls1021a-extirq
- fsl,ls1043a-extirq
- fsl,ls1088a-extirq
- items:
- enum:
- fsl,ls1046a-extirq
- const: fsl,ls1043a-extirq
- items:
- enum:
- fsl,ls2080a-extirq
- fsl,lx2160a-extirq
- const: fsl,ls1088a-extirq
'#interrupt-cells':
const: 2
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
description:
Specifies the Interrupt Polarity Control Register (INTPCR) in the
SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
interrupt-map:
description: Specifies the mapping from external interrupts to GIC interrupts.
interrupt-map-mask: true
required:
- compatible
- '#interrupt-cells'
- '#address-cells'
- interrupt-controller
- reg
- interrupt-map
- interrupt-map-mask
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,ls1021a-extirq
then:
properties:
interrupt-map:
minItems: 6
maxItems: 6
interrupt-map-mask:
items:
- const: 0x7
- const: 0
- if:
properties:
compatible:
contains:
enum:
- fsl,ls1043a-extirq
- fsl,ls1046a-extirq
- fsl,ls1088a-extirq
- fsl,ls2080a-extirq
- fsl,lx2160a-extirq
then:
properties:
interrupt-map:
minItems: 12
maxItems: 12
interrupt-map-mask:
items:
- const: 0xf
- const: 0
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
interrupt-controller@1ac {
compatible = "fsl,ls1021a-extirq";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1ac 4>;
interrupt-map =
<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0x7 0x0>;
};

5
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
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@ -21,8 +21,9 @@ Properties:
- "qcom,sc7180-pdc": For SC7180
- "qcom,sc7280-pdc": For SC7280
- "qcom,sdm845-pdc": For SDM845
- "qcom,sdm8250-pdc": For SM8250
- "qcom,sdm8350-pdc": For SM8350
- "qcom,sm6350-pdc": For SM6350
- "qcom,sm8250-pdc": For SM8250
- "qcom,sm8350-pdc": For SM8350
- reg:
Usage: required

16
Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
View File

@ -37,12 +37,18 @@ properties:
hardware supports just a single, combined interrupt line.
If provided, then the combined interrupt will be used in preference to
any others.
- minItems: 2
- minItems: 1
items:
- const: eventq # Event Queue not empty
- const: gerror # Global Error activated
- const: priq # PRI Queue not empty
- const: cmdq-sync # CMD_SYNC complete
- enum:
- eventq # Event Queue not empty
- gerror # Global Error activated
- const: gerror
- enum:
- cmdq-sync # CMD_SYNC complete
- priq # PRI Queue not empty
- enum:
- cmdq-sync
- priq
'#iommu-cells':
const: 1

1
Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml
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@ -107,4 +107,3 @@ examples:
power-domains = <&pd_gsc>;
#iommu-cells = <0>;
};

2
Documentation/devicetree/bindings/leds/backlight/qcom-wled.yaml
View File

@ -81,7 +81,7 @@ properties:
description: |
kHz; switching frequency.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, 1600, 1920,
enum: [ 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, 1600, 1920,
2400, 3200, 4800, 9600 ]
qcom,ovp:

2
Documentation/devicetree/bindings/leds/leds-mt6360.yaml
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@ -11,7 +11,7 @@ maintainers:
description: |
This module is part of the MT6360 MFD device.
see Documentation/devicetree/bindings/mfd/mt6360.yaml
see Documentation/devicetree/bindings/mfd/mediatek,mt6360.yaml
Add MT6360 LED driver include 2-channel Flash LED with torch/strobe mode,
and 4-channel RGB LED support Register/Flash/Breath Mode

1
Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
View File

@ -51,4 +51,3 @@ examples:
interrupts = <208>, <209>, <210>;
#mbox-cells = <1>;
};

1
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
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@ -27,6 +27,7 @@ properties:
- qcom,sm6350-ipcc
- qcom,sm8250-ipcc
- qcom,sm8350-ipcc
- qcom,sm8450-ipcc
- qcom,sc7280-ipcc
- const: qcom,ipcc

127
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
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@ -1,127 +0,0 @@
Xilinx IPI Mailbox Controller
========================================
The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
agent owns registers used for notification and buffers for message.
+-------------------------------------+
| Xilinx ZynqMP IPI Controller |
+-------------------------------------+
+--------------------------------------------------+
ATF | |
| |
| |
+--------------------------+ |
| |
| |
+--------------------------------------------------+
+------------------------------------------+
| +----------------+ +----------------+ |
Hardware | | IPI Agent | | IPI Buffers | |
| | Registers | | | |
| | | | | |
| +----------------+ +----------------+ |
| |
| Xilinx IPI Agent Block |
+------------------------------------------+
Controller Device Node:
===========================
Required properties:
--------------------
IPI agent node:
- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
- interrupt-parent: Phandle for the interrupt controller
- interrupts: Interrupt information corresponding to the
interrupt-names property.
- xlnx,ipi-id: local Xilinx IPI agent ID
- #address-cells: number of address cells of internal IPI mailbox nodes
- #size-cells: number of size cells of internal IPI mailbox nodes
Internal IPI mailbox node:
- reg: IPI buffers address ranges
- reg-names: Names of the reg resources. It should have:
* local_request_region
- IPI request msg buffer written by local and read
by remote
* local_response_region
- IPI response msg buffer written by local and read
by remote
* remote_request_region
- IPI request msg buffer written by remote and read
by local
* remote_response_region
- IPI response msg buffer written by remote and read
by local
- #mbox-cells: Shall be 1. It contains:
* tx(0) or rx(1) channel
- xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
connected to.
Optional properties:
--------------------
- method: The method of accessing the IPI agent registers.
Permitted values are: "smc" and "hvc". Default is
"smc".
Client Device Node:
===========================
Required properties:
--------------------
- mboxes: Standard property to specify a mailbox
(See ./mailbox.txt)
- mbox-names: List of identifier strings for each mailbox
channel.
Example:
===========================
zynqmp_ipi {
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
interrupts = <0 29 4>;
xlnx,ipi-id = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* APU<->RPU0 IPI mailbox controller */
ipi_mailbox_rpu0: mailbox@ff990400 {
reg = <0xff990400 0x20>,
<0xff990420 0x20>,
<0xff990080 0x20>,
<0xff9900a0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <1>;
};
/* APU<->RPU1 IPI mailbox controller */
ipi_mailbox_rpu1: mailbox@ff990440 {
reg = <0xff990440 0x20>,
<0xff990460 0x20>,
<0xff990280 0x20>,
<0xff9902a0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <2>;
};
};
rpu0 {
...
mboxes = <&ipi_mailbox_rpu0 0>,
<&ipi_mailbox_rpu0 1>;
mbox-names = "tx", "rx";
};
rpu1 {
...
mboxes = <&ipi_mailbox_rpu1 0>,
<&ipi_mailbox_rpu1 1>;
mbox-names = "tx", "rx";
};

140
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@ -0,0 +1,140 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
description: |
The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
agent owns registers used for notification and buffers for message.
+-------------------------------------+
| Xilinx ZynqMP IPI Controller |
+-------------------------------------+
+--------------------------------------------------+
TF-A | |
| |
| |
+--------------------------+ |
| |
| |
+--------------------------------------------------+
+------------------------------------------+
| +----------------+ +----------------+ |
Hardware | | IPI Agent | | IPI Buffers | |
| | Registers | | | |
| | | | | |
| +----------------+ +----------------+ |
| |
| Xilinx IPI Agent Block |
+------------------------------------------+
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
properties:
compatible:
const: xlnx,zynqmp-ipi-mailbox
method:
description: |
The method of calling the PM-API firmware layer.
Permitted values are.
- "smc" : SMC #0, following the SMCCC
- "hvc" : HVC #0, following the SMCCC
$ref: /schemas/types.yaml#/definitions/string
enum:
- smc
- hvc
default: smc
'#address-cells':
const: 2
'#size-cells':
const: 2
xlnx,ipi-id:
description: |
Remote Xilinx IPI agent ID of which the mailbox is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
interrupts:
maxItems: 1
ranges: true
patternProperties:
'^mailbox@[0-9a-f]+$':
description: Internal ipi mailbox node
type: object # DT nodes are json objects
properties:
xlnx,ipi-id:
description:
Remote Xilinx IPI agent ID of which the mailbox is connected to.
$ref: /schemas/types.yaml#/definitions/uint32
'#mbox-cells':
const: 1
description:
It contains tx(0) or rx(1) channel IPI id number.
reg:
maxItems: 4
reg-names:
items:
- const: local_request_region
- const: local_response_region
- const: remote_request_region
- const: remote_response_region
required:
- reg
- reg-names
- "#mbox-cells"
additionalProperties: false
required:
- compatible
- interrupts
- '#address-cells'
- '#size-cells'
- xlnx,ipi-id
examples:
- |
#include<dt-bindings/interrupt-controller/arm-gic.h>
amba {
#address-cells = <0x2>;
#size-cells = <0x2>;
zynqmp-mailbox {
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
xlnx,ipi-id = <0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
mailbox: mailbox@ff9905c0 {
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
<0x0 0xff990ea0 0x0 0x20>;
reg-names = "local_request_region",
"local_response_region",
"remote_request_region",
"remote_response_region";
#mbox-cells = <1>;
xlnx,ipi-id = <4>;
};
};
};
...

3
Documentation/devicetree/bindings/media/i2c/adv7604.yaml
View File

@ -60,7 +60,8 @@ properties:
enables hot-plug detection.
default-input:
maxItems: 1
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]
description:
Select which input is selected after reset.

1
Documentation/devicetree/bindings/media/microchip,xisc.yaml
View File

@ -126,4 +126,3 @@ examples:
};
};
};

256
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@ -0,0 +1,256 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/mediatek,mt6360.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MT6360 PMIC from MediaTek Integrated
maintainers:
- Gene Chen <gene_chen@richtek.com>
description: |
MT6360 is a PMIC device with the following sub modules.
It is interfaced to host controller using I2C interface.
This document describes the binding for PMIC device and its sub module.
properties:
compatible:
const: mediatek,mt6360
reg:
maxItems: 1
wakeup-source: true
interrupts:
maxItems: 1
interrupt-names:
const: IRQB
interrupt-controller: true
"#interrupt-cells":
const: 1
description:
The first cell is the IRQ number.
regulators:
$ref: /schemas/regulator/mt6360-regulator.yaml#
charger:
$ref: /schemas/power/supply/mt6360_charger.yaml#
tcpc:
$ref: /schemas/usb/mediatek,mt6360-tcpc.yaml#
led-controller:
$ref: /schemas/leds/leds-mt6360.yaml#
required:
- compatible
- reg
- interrupts
- interrupt-controller
- "#interrupt-cells"
additionalProperties:
type: object
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@34 {
compatible = "mediatek,mt6360";
reg = <0x34>;
wakeup-source;
interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "IRQB";
interrupt-controller;
#interrupt-cells = <1>;
mt6360_charger: charger {
compatible = "mediatek,mt6360-chg";
richtek,vinovp-microvolt = <14500000>;
otg_vbus_regulator: usb-otg-vbus-regulator {
regulator-compatible = "usb-otg-vbus";
regulator-name = "usb-otg-vbus";
regulator-min-microvolt = <4425000>;
regulator-max-microvolt = <5825000>;
};
};
led-controller {
compatible = "mediatek,mt6360-led";
#address-cells = <1>;
#size-cells = <0>;
multi-led@0 {
reg = <0>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_RGB>;
led-max-microamp = <24000>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
led@3 {
reg = <3>;
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_WHITE>;
led-max-microamp = <150000>;
};
led@4 {
reg = <4>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <1>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
led@5 {
reg = <5>;
function = LED_FUNCTION_FLASH;
color = <LED_COLOR_ID_WHITE>;
function-enumerator = <2>;
led-max-microamp = <200000>;
flash-max-microamp = <500000>;
flash-max-timeout-us = <1024000>;
};
};
regulators {
compatible = "mediatek,mt6360-regulator";
LDO_VIN3-supply = <&BUCK2>;
buck1 {
regulator-compatible = "BUCK1";
regulator-name = "mt6360,buck1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP
MT6360_OPMODE_ULP>;
};
BUCK2: buck2 {
regulator-compatible = "BUCK2";
regulator-name = "mt6360,buck2";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP
MT6360_OPMODE_ULP>;
};
ldo6 {
regulator-compatible = "LDO6";
regulator-name = "mt6360,ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo7 {
regulator-compatible = "LDO7";
regulator-name = "mt6360,ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo1 {
regulator-compatible = "LDO1";
regulator-name = "mt6360,ldo1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo2 {
regulator-compatible = "LDO2";
regulator-name = "mt6360,ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo3 {
regulator-compatible = "LDO3";
regulator-name = "mt6360,ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
ldo5 {
regulator-compatible = "LDO5";
regulator-name = "mt6360,ldo5";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
regulator-allowed-modes = <MT6360_OPMODE_NORMAL
MT6360_OPMODE_LP>;
};
};
tcpc {
compatible = "mediatek,mt6360-tcpc";
interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "PD_IRQB";
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>;
op-sink-microwatt = <10000000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&usb_hs>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&usb_ss>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&dp_aux>;
};
};
};
};
};
};
};

2
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
View File

@ -59,7 +59,7 @@ Required properties for peripheral child nodes:
Optional properties for peripheral child nodes:
- interrupts: Interrupts are specified as a 4-tuple. For more information
see:
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
- interrupt-names: Corresponding interrupt name to the interrupts property
Each child node of SPMI slave id represents a function of the PMIC. In the

1
Documentation/devicetree/bindings/mtd/common.txt
View File

@ -1 +0,0 @@
This file has been moved to mtd.yaml.

2
Documentation/devicetree/bindings/mtd/hisilicon,fmc-spi-nor.txt
View File

@ -17,7 +17,7 @@ spi-nor-controller@10000000 {
reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
reg-names = "control", "memory";
clocks = <&clock HI3519_FMC_CLK>;
spi-nor@0 {
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};

8
Documentation/devicetree/bindings/mux/reg-mux.yaml
View File

@ -25,8 +25,12 @@ properties:
const: 1
mux-reg-masks:
description: an array of register offset and pre-shifted bitfield mask
pairs, each describing a single mux control.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: register offset
- description: pre-shifted bitfield mask
description: Each entry pair describes a single mux control.
idle-states: true

68
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/asix,ax88178.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: The device tree bindings for the USB Ethernet controllers
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
description: |
Device tree properties for hard wired USB Ethernet devices.
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
items:
- enum:
- usbb95,1720 # ASIX AX88172
- usbb95,172a # ASIX AX88172A
- usbb95,1780 # ASIX AX88178
- usbb95,7720 # ASIX AX88772
- usbb95,772a # ASIX AX88772A
- usbb95,772b # ASIX AX88772B
- usbb95,7e2b # ASIX AX88772B
reg: true
local-mac-address: true
mac-address: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
usb {
#address-cells = <1>;
#size-cells = <0>;
ethernet@1 {
compatible = "usbb95,7e2b";
reg = <1>;
local-mac-address = [00 00 00 00 00 00];
};
};
- |
usb {
#address-cells = <1>;
#size-cells = <0>;
usb1@1 {
compatible = "usb1234,5678";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethernet@1 {
compatible = "usbb95,772b";
reg = <1>;
};
};
};

1
Documentation/devicetree/bindings/net/cdns,macb.yaml
View File

@ -122,6 +122,7 @@ patternProperties:
reset-gpios: true
magic-packet:
type: boolean
description:
Indicates that the hardware supports waking up via magic packet.

1
Documentation/devicetree/bindings/net/ingenic,mac.yaml
View File

@ -37,6 +37,7 @@ properties:
const: stmmaceth
mode-reg:
$ref: /schemas/types.yaml#/definitions/phandle
description: An extra syscon register that control ethernet interface and timing delay
rx-clk-delay-ps:

63
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,lan95xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: The device tree bindings for the USB Ethernet controllers
maintainers:
- Oleksij Rempel <o.rempel@pengutronix.de>
description: |
Device tree properties for hard wired SMSC95xx compatible USB Ethernet
controller.
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
items:
- enum:
- usb424,9500 # SMSC9500 USB Ethernet Device
- usb424,9505 # SMSC9505 USB Ethernet Device
- usb424,9530 # SMSC LAN9530 USB Ethernet Device
- usb424,9730 # SMSC LAN9730 USB Ethernet Device
- usb424,9900 # SMSC9500 USB Ethernet Device (SAL10)
- usb424,9901 # SMSC9505 USB Ethernet Device (SAL10)
- usb424,9902 # SMSC9500A USB Ethernet Device (SAL10)
- usb424,9903 # SMSC9505A USB Ethernet Device (SAL10)
- usb424,9904 # SMSC9512/9514 USB Hub & Ethernet Device (SAL10)
- usb424,9905 # SMSC9500A USB Ethernet Device (HAL)
- usb424,9906 # SMSC9505A USB Ethernet Device (HAL)
- usb424,9907 # SMSC9500 USB Ethernet Device (Alternate ID)
- usb424,9908 # SMSC9500A USB Ethernet Device (Alternate ID)
- usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Devic. ID)
- usb424,9e00 # SMSC9500A USB Ethernet Device
- usb424,9e01 # SMSC9505A USB Ethernet Device
- usb424,9e08 # SMSC LAN89530 USB Ethernet Device
- usb424,ec00 # SMSC9512/9514 USB Hub & Ethernet Device
reg: true
local-mac-address: true
mac-address: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
usb {
#address-cells = <1>;
#size-cells = <0>;
ethernet@1 {
compatible = "usb424,9e00";
reg = <1>;
local-mac-address = [00 00 00 00 00 00];
};
};

7
Documentation/devicetree/bindings/net/qcom,ipa.yaml
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@ -182,6 +182,12 @@ examples:
smp2p-mpss {
compatible = "qcom,smp2p";
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 6>;
qcom,smem = <94>, <432>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
ipa_smp2p_out: ipa-ap-to-modem {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
@ -193,6 +199,7 @@ examples:
#interrupt-cells = <2>;
};
};
ipa@1e40000 {
compatible = "qcom,sdm845-ipa";

61
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
maintainers:
- Nicolas Pitre <nico@fluxnic.net>
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
const: smsc,lan91c111
reg:
maxItems: 1
interrupts:
maxItems: 1
reg-shift: true
reg-io-width:
enum: [ 1, 2, 4 ]
default: 4
reset-gpios:
description: GPIO connected to control RESET pin
maxItems: 1
power-gpios:
description: GPIO connect to control PWRDWN pin
maxItems: 1
pxa-u16-align4:
description: put in place the workaround the force all u16 writes to be
32 bits aligned
type: boolean
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
ethernet@4010000 {
compatible = "smsc,lan91c111";
reg = <0x40100000 0x10000>;
phy-mode = "mii";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <2>;
};

17
Documentation/devicetree/bindings/net/smsc-lan91c111.txt
View File

@ -1,17 +0,0 @@
SMSC LAN91c111 Ethernet mac
Required properties:
- compatible = "smsc,lan91c111";
- reg : physical address and size of registers
- interrupts : interrupt connection
Optional properties:
- phy-device : see ethernet.txt file in the same directory
- reg-io-width : Mask of sizes (in bytes) of the IO accesses that
are supported on the device. Valid value for SMSC LAN91c111 are
1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning
16-bit access only.
- power-gpios: GPIO to control the PWRDWN pin
- reset-gpios: GPIO to control the RESET pin
- pxa-u16-align4 : Boolean, put in place the workaround the force all
u16 writes to be 32 bits aligned

1
Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml
View File

@ -34,6 +34,7 @@ properties:
maxItems: 1
bus_freq:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 2500000
description: MDIO Bus frequency

1
Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
View File

@ -142,4 +142,3 @@ examples:
assigned-clock-parents = <&k3_clks 118 11>;
};
};

2
Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml
View File

@ -384,7 +384,7 @@ examples:
pcie0 {
#size-cells = <2>;
#address-cells = <3>;
wifi_0: wifi@0 {
reg = <0 0 0 0 0>;
memory-region = <&qcn9074_0>;

2
Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml
View File

@ -54,9 +54,11 @@ properties:
ref-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: Reference clock frequency.
tcxo-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: TCXO clock frequency.
clock-xtal:

4
Documentation/devicetree/bindings/nvmem/snvs-lpgpr.yaml
View File

@ -15,6 +15,10 @@ properties:
- fsl,imx6q-snvs-lpgpr
- fsl,imx6ul-snvs-lpgpr
- fsl,imx7d-snvs-lpgpr
- fsl,imx8mm-snvs-lpgpr
- fsl,imx8mn-snvs-lpgpr
- fsl,imx8mp-snvs-lpgpr
- fsl,imx8mq-snvs-lpgpr
required:
- compatible

6
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
View File

@ -55,13 +55,15 @@ properties:
Translation Unit) registers.
num-ib-windows:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 256
description: number of inbound address translation windows
maxItems: 1
deprecated: true
num-ob-windows:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 256
description: number of outbound address translation windows
maxItems: 1
deprecated: true
required:

2
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
View File

@ -68,6 +68,8 @@ properties:
Translation Unit) registers.
num-viewport:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 256
description: |
number of view ports configured in hardware. If a platform
does not specify it, the driver autodetects it.

96
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@ -0,0 +1,96 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext UniPhier PCIe host controller
description: |
UniPhier PCIe host controller is based on the Synopsys DesignWare
PCI core. It shares common features with the PCIe DesignWare core and
inherits common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
enum:
- socionext,uniphier-pcie
reg:
minItems: 3
maxItems: 4
reg-names:
minItems: 3
items:
- const: dbi
- const: link
- const: config
- const: atu
clocks:
maxItems: 1
resets:
maxItems: 1
num-viewport: true
num-lanes: true
phys:
maxItems: 1
phy-names:
const: pcie-phy
required:
- compatible
- reg
- reg-names
- clocks
- resets
unevaluatedProperties: false
examples:
- |
pcie: pcie@66000000 {
compatible = "socionext,uniphier-pcie";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
#address-cells = <3>;
#size-cells = <2>;
clocks = <&sys_clk 24>;
resets = <&sys_rst 24>;
num-lanes = <1>;
num-viewport = <1>;
bus-range = <0x0 0xff>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
<0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
phy-names = "pcie-phy";
phys = <&pcie_phy>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
interrupts = <0 224 4>, <0 225 4>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <0 226 4>;
};
};

82
Documentation/devicetree/bindings/pci/uniphier-pcie.txt
View File

@ -1,82 +0,0 @@
Socionext UniPhier PCIe host controller bindings
This describes the devicetree bindings for PCIe host controller implemented
on Socionext UniPhier SoCs.
UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
It shares common functions with the PCIe DesignWare core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
Required properties:
- compatible: Should be "socionext,uniphier-pcie".
- reg: Specifies offset and length of the register set for the device.
According to the reg-names, appropriate register sets are required.
- reg-names: Must include the following entries:
"dbi" - controller configuration registers
"link" - SoC-specific glue layer registers
"config" - PCIe configuration space
"atu" - iATU registers for DWC version 4.80 or later
- clocks: A phandle to the clock gate for PCIe glue layer including
the host controller.
- resets: A phandle to the reset line for PCIe glue layer including
the host controller.
- interrupts: A list of interrupt specifiers. According to the
interrupt-names, appropriate interrupts are required.
- interrupt-names: Must include the following entries:
"dma" - DMA interrupt
"msi" - MSI interrupt
Optional properties:
- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
phys are required.
- phy-names: Must be "pcie-phy".
Required sub-node:
- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI
interrupts.
Required properties for legacy-interrupt-controller:
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: specifies the number of cells needed to encode an
interrupt source. The value must be 1.
- interrupt-parent: Phandle to the parent interrupt controller.
- interrupts: An interrupt specifier for legacy interrupt.
Example:
pcie: pcie@66000000 {
compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
<0x2fff0000 0x10000>;
#address-cells = <3>;
#size-cells = <2>;
clocks = <&sys_clk 24>;
resets = <&sys_rst 24>;
num-lanes = <1>;
num-viewport = <1>;
bus-range = <0x0 0xff>;
device_type = "pci";
ranges =
/* downstream I/O */
<0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
/* non-prefetchable memory */
0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
interrupts = <0 224 4>, <0 225 4>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
<0 0 0 3 &pcie_intc 2>, /* INTC */
<0 0 0 4 &pcie_intc 3>; /* INTD */
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <0 226 4>;
};
};

40
Documentation/devicetree/bindings/perf/spe-pmu.yaml Normal file
View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
maintainers:
- Will Deacon <will@kernel.org>
description:
ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
performance sample data using an in-memory trace buffer.
properties:
compatible:
const: arm,statistical-profiling-extension-v1
interrupts:
maxItems: 1
description: |
The PPI to signal SPE events. For heterogeneous systems where SPE is only
supported on a subset of the CPUs, please consult the arm,gic-v3 binding
for details on describing a PPI partition.
additionalProperties: false
required:
- compatible
- interrupts
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};

2
Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
View File

@ -120,6 +120,7 @@ patternProperties:
input-schmitt-disable: true
input-polarity-invert:
type: boolean
description:
Enable or disable pin input polarity inversion.
@ -132,6 +133,7 @@ patternProperties:
output-low: true
output-polarity-invert:
type: boolean
description:
Enable or disable pin output polarity inversion.

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