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m68k: Assorted spelling fixes
- s/acccess/access/ - s/accoding/according/ - s/addad/added/ - s/addreess/address/ - s/allocatiom/allocation/ - s/Assember/Assembler/ - s/compactnes/compactness/ - s/conneced/connected/ - s/decending/descending/ - s/diectly/directly/ - s/diplacement/displacement/ Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> [geert: Squashed, fix arch/m68k/ifpsp060/src/pfpsp.S] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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@ -288,7 +288,7 @@ _clear_bss:
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#endif
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/*
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* Assember start up done, start code proper.
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* Assembler start up done, start code proper.
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*/
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jsr start_kernel /* start Linux kernel */
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@ -111,7 +111,7 @@ void __init config_BSP(char *commandp, int size)
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/***************************************************************************/
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/*
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* Some 5272 based boards have the FEC ethernet diectly connected to
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* Some 5272 based boards have the FEC ethernet directly connected to
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* an ethernet switch. In this case we need to use the fixed phy type,
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* and we need to declare it early in boot.
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*/
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@ -42,7 +42,7 @@ static unsigned long iospace;
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/*
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* We need to be carefull probing on bus 0 (directly connected to host
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* bridge). We should only acccess the well defined possible devices in
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* bridge). We should only access the well defined possible devices in
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* use, ignore aliases and the like.
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*/
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static unsigned char mcf_host_slot2sid[32] = {
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@ -10191,7 +10191,7 @@ xdnrm_con:
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xdnrm_sd:
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mov.l %a1,-(%sp)
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tst.b LOCAL_EX(%a0) # is denorm pos or neg?
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smi.b %d1 # set d0 accodingly
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smi.b %d1 # set d0 accordingly
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bsr.l unf_sub
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mov.l (%sp)+,%a1
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xdnrm_exit:
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@ -10990,7 +10990,7 @@ src_qnan_m:
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# routines where an instruction is selected by an index into
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# a large jump table corresponding to a given instruction which
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# has been decoded. Flow continues here where we now decode
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# further accoding to the source operand type.
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# further according to the source operand type.
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#
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global fsinh
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@ -23196,14 +23196,14 @@ m_sign:
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#
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# 1. Branch on the sign of the adjusted exponent.
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# 2p.(positive exp)
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# 2. Check M16 and the digits in lwords 2 and 3 in decending order.
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# 2. Check M16 and the digits in lwords 2 and 3 in descending order.
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# 3. Add one for each zero encountered until a non-zero digit.
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# 4. Subtract the count from the exp.
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# 5. Check if the exp has crossed zero in #3 above; make the exp abs
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# and set SE.
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# 6. Multiply the mantissa by 10**count.
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# 2n.(negative exp)
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# 2. Check the digits in lwords 3 and 2 in decending order.
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# 2. Check the digits in lwords 3 and 2 in descending order.
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# 3. Add one for each zero encountered until a non-zero digit.
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# 4. Add the count to the exp.
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# 5. Check if the exp has crossed zero in #3 above; clear SE.
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@ -13156,14 +13156,14 @@ m_sign:
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#
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# 1. Branch on the sign of the adjusted exponent.
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# 2p.(positive exp)
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# 2. Check M16 and the digits in lwords 2 and 3 in decending order.
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# 2. Check M16 and the digits in lwords 2 and 3 in descending order.
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# 3. Add one for each zero encountered until a non-zero digit.
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# 4. Subtract the count from the exp.
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# 5. Check if the exp has crossed zero in #3 above; make the exp abs
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# and set SE.
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# 6. Multiply the mantissa by 10**count.
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# 2n.(negative exp)
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# 2. Check the digits in lwords 3 and 2 in decending order.
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# 2. Check the digits in lwords 3 and 2 in descending order.
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# 3. Add one for each zero encountered until a non-zero digit.
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# 4. Add the count to the exp.
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# 5. Check if the exp has crossed zero in #3 above; clear SE.
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@ -18,7 +18,7 @@
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* AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
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* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
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*
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* AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
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* AUG/25/2000 : added support for 8, 16 and 32-bit Single-Address-Mode (K)2000
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* Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
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*
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* APR/18/2002 : added proper support for MCF5272 DMA controller.
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@ -123,10 +123,10 @@
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/*
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* I2C module.
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*/
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#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base addreess I2C0 */
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#define MCFI2C_BASE0 (MCF_MBAR + 0x280) /* Base address I2C0 */
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#define MCFI2C_SIZE0 0x20 /* Register set size */
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#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base addreess I2C1 */
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#define MCFI2C_BASE1 (MCF_MBAR2 + 0x440) /* Base address I2C1 */
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#define MCFI2C_SIZE1 0x20 /* Register set size */
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/*
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@ -38,7 +38,7 @@
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/*
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* MMU Operation register.
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*/
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#define MMUOR_UAA 0x00000001 /* Update allocatiom address */
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#define MMUOR_UAA 0x00000001 /* Update allocation address */
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#define MMUOR_ACC 0x00000002 /* TLB access */
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#define MMUOR_RD 0x00000004 /* TLB access read */
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#define MMUOR_WR 0x00000000 /* TLB access write */
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@ -1,6 +1,6 @@
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/*
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* Q40 master Chip Control
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* RTC stuff merged for compactnes..
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* RTC stuff merged for compactness.
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*/
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#ifndef _Q40_MASTER_H
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@ -60,7 +60,7 @@
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*
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* The host talks to the IOPs using a rather simple message-passing scheme via
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* a shared memory area in the IOP RAM. Each IOP has seven "channels"; each
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* channel is conneced to a specific software driver on the IOP. For example
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* channel is connected to a specific software driver on the IOP. For example
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* on the SCC IOP there is one channel for each serial port. Each channel has
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* an incoming and and outgoing message queue with a depth of one.
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*
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@ -130,7 +130,7 @@ do_fscc=0
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bfextu %d2{#13,#3},%d0
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.endm
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| decode the 8bit diplacement from the brief extension word
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| decode the 8bit displacement from the brief extension word
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.macro fp_decode_disp8
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move.b %d2,%d0
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ext.w %d0
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