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irqchip/gic: Support RealView variant setup
The ARM RealView PB11MPCore reference design has some special bits in a system controller register to set up the GIC in one of three modes: legacy, new with DCC, new without DCC. The register is also used to enable FIQ. Since the platform will not boot unless this register is set up to "new with DCC" mode, we need a special quirk to be compiled-in for the RealView platforms. If we find the right compatible string on the GIC TestChip, we enable this quirk by looking up the system controller and enabling the special bits. We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old boardfile code has the same fix hardcoded, and this is only needed for the attempts to modernize the RealView code using device tree. After fixing this, the PB11MPCore boots with device tree only. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
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obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
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obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
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obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
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obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o
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obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
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obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
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obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
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43
drivers/irqchip/irq-gic-realview.c
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43
drivers/irqchip/irq-gic-realview.c
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@ -0,0 +1,43 @@
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/*
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* Special GIC quirks for the ARM RealView
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* Copyright (C) 2015 Linus Walleij
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*/
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/bitops.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#define REALVIEW_SYS_LOCK_OFFSET 0x20
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#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74
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#define VERSATILE_LOCK_VAL 0xA05F
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#define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24)
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#define PLD_INTMODE_LEGACY 0x0
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#define PLD_INTMODE_NEW_DCC BIT(22)
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#define PLD_INTMODE_NEW_NO_DCC BIT(23)
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#define PLD_INTMODE_FIQ_ENABLE BIT(24)
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static int __init
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realview_gic_of_init(struct device_node *node, struct device_node *parent)
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{
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static struct regmap *map;
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/* The PB11MPCore GIC needs to be configured in the syscon */
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map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon");
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if (!IS_ERR(map)) {
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/* new irq mode with no DCC */
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regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
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VERSATILE_LOCK_VAL);
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regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1,
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PLD_INTMODE_NEW_NO_DCC,
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PLD_INTMODE_MASK);
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regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000);
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pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n");
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} else {
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pr_err("TC11MP GIC setup: could not find syscon\n");
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return -ENXIO;
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}
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return gic_of_init(node, parent);
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}
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IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
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@ -1196,7 +1196,7 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
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return true;
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}
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static int __init
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int __init
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gic_of_init(struct device_node *node, struct device_node *parent)
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{
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void __iomem *cpu_base;
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@ -103,6 +103,16 @@ struct device_node;
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void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
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int gic_cpu_if_down(unsigned int gic_nr);
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/*
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* Subdrivers that need some preparatory work can initialize their
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* chips and call this to register their GICs.
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*/
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int gic_of_init(struct device_node *node, struct device_node *parent);
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/*
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* Legacy platforms not converted to DT yet must use this to init
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* their GIC
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*/
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void gic_init(unsigned int nr, int start,
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void __iomem *dist , void __iomem *cpu);
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