mirror of
https://github.com/edk2-porting/linux-next.git
synced 2025-01-09 22:24:04 +08:00
arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards
Kontron Electronics GmbH offers small and powerful SoMs based on the i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR. The matching baseboards have the same form factor and similar interfaces as the other boards from the Kontron "Board-Line" family, including SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232, RS485, CAN, LVDS or HDMI, RTC and much more. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Frieder Schrempf
Shawn Guo
parent
c13a7d84c4
commit
8668d8b2e6
@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dts
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
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322
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
Normal file
322
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
Normal file
@ -0,0 +1,322 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright (C) 2019 Kontron Electronics GmbH
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*/
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/dts-v1/;
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#include "imx8mm-kontron-n801x-som.dtsi"
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/ {
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model = "Kontron i.MX8MM N801X S";
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compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
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aliases {
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ethernet1 = &usbnet;
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};
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/* fixed crystal dedicated to mcp2515 */
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osc_can: clock-osc-can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <16000000>;
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clock-output-names = "osc-can";
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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led1 {
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label = "led1";
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gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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led2 {
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label = "led2";
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gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
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};
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led3 {
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label = "led3";
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gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
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};
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led4 {
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label = "led4";
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gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
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};
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led5 {
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label = "led5";
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gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
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};
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led6 {
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label = "led6";
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gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
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};
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};
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pwm-beeper {
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compatible = "pwm-beeper";
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pwms = <&pwm2 0 5000 0>;
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};
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reg_rst_eth2: regulator-rst-eth2 {
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compatible = "regulator-fixed";
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regulator-name = "rst-usb-eth2";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_eth2>;
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gpio = <&gpio3 2 GPIO_ACTIVE_LOW>;
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};
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reg_vdd_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "vdd-5v";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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};
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
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status = "okay";
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can0: can@0 {
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compatible = "microchip,mcp2515";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can>;
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clocks = <&osc_can>;
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interrupt-parent = <&gpio4>;
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interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
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spi-max-frequency = <100000>;
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vdd-supply = <®_vdd_3v3>;
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xceiver-supply = <®_vdd_5v>;
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};
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};
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&ecspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi3>;
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cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-connection-type = "rgmii";
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phy-handle = <ðphy>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@0 {
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reg = <0>;
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reset-assert-us = <100>;
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reset-deassert-us = <100>;
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reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&i2c4 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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rtc@32 {
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compatible = "epson,rx8900";
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reg = <0x32>;
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};
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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uart-has-rtscts;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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linux,rs485-enabled-at-boot-time;
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uart-has-rtscts;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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over-current-active-low;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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usb1@1 {
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compatible = "usb424,9514";
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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usbnet: usbether@1 {
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compatible = "usb424,ec00";
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reg = <1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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};
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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vmmc-supply = <®_vdd_3v3>;
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vqmmc-supply = <®_nvcc_sd>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio>;
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pinctrl_can: cangrp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
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MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
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MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
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MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
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>;
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};
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pinctrl_ecspi3: ecspi3grp {
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fsl,pins = <
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MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
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MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
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MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
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MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
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MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
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>;
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};
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pinctrl_gpio_led: gpioledgrp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
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MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
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MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
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MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
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MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
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MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
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MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
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>;
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};
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pinctrl_gpio: gpiogrp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
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MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
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MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
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MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
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MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
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MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
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MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
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MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
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>;
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};
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pinctrl_pwm2: pwm2grp {
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fsl,pins = <
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MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
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MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
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MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
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MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
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MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
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MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
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MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
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>;
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};
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pinctrl_usb_eth2: usbeth2grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
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MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
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MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
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MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
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MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
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MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
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MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
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>;
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};
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};
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294
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
Normal file
294
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
Normal file
@ -0,0 +1,294 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright (C) 2019 Kontron Electronics GmbH
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*/
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#include "imx8mm.dtsi"
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/ {
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model = "Kontron i.MX8MM N801X SoM";
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compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
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memory@40000000 {
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device_type = "memory";
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/*
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* There are multiple SoM flavors with different DDR sizes.
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* The smallest is 1GB. For larger sizes the bootloader will
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* update the reg property.
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*/
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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chosen {
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stdout-path = &uart3;
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};
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};
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&A53_0 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_1 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_2 {
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cpu-supply = <®_vdd_arm>;
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};
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&A53_3 {
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cpu-supply = <®_vdd_arm>;
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25M {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100M {
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opp-hz = /bits/ 64 <100000000>;
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};
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opp-750M {
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opp-hz = /bits/ 64 <750000000>;
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};
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};
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
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status = "okay";
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spi-flash@0 {
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compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
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spi-max-frequency = <80000000>;
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reg = <0>;
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pca9450: pmic@25 {
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compatible = "nxp,pca9450a";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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reg_vdd_soc: BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
|
||||
reg_vdd_arm: BUCK2 {
|
||||
regulator-name = "buck2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-boot-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
};
|
||||
|
||||
reg_vdd_dram: BUCK3 {
|
||||
regulator-name = "buck3";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_3v3: BUCK4 {
|
||||
regulator-name = "buck4";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_1v8: BUCK5 {
|
||||
regulator-name = "buck5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_nvcc_dram: BUCK6 {
|
||||
regulator-name = "buck6";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_nvcc_snvs: LDO1 {
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_snvs: LDO2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdda: LDO3 {
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_vdd_phy: LDO4 {
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_nvcc_sd: LDO5 {
|
||||
regulator-name = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart3 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
vmmc-supply = <®_vdd_3v3>;
|
||||
vqmmc-supply = <®_vdd_1v8>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_ecspi1: ecspi1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
|
||||
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user