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crypto: arm - add support for SHA1 using ARMv8 Crypto Instructions
This implements the SHA1 secure hash algorithm using the AArch32 versions of the ARMv8 Crypto Extensions for SHA1. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ard Biesheuvel
Herbert Xu
parent
652ccae5cc
commit
864cbeed4a
@ -27,6 +27,16 @@ config CRYPTO_SHA1_ARM_NEON
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using optimized ARM NEON assembly, when NEON instructions are
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available.
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config CRYPTO_SHA1_ARM_CE
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tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)"
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depends on KERNEL_MODE_NEON
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select CRYPTO_SHA1_ARM
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select CRYPTO_SHA1
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select CRYPTO_HASH
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help
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SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented
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using special ARMv8 Crypto Extensions.
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config CRYPTO_SHA512_ARM_NEON
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tristate "SHA384 and SHA512 digest algorithm (ARM NEON)"
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depends on KERNEL_MODE_NEON
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@ -7,12 +7,14 @@ obj-$(CONFIG_CRYPTO_AES_ARM_BS) += aes-arm-bs.o
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obj-$(CONFIG_CRYPTO_SHA1_ARM) += sha1-arm.o
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obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o
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obj-$(CONFIG_CRYPTO_SHA512_ARM_NEON) += sha512-arm-neon.o
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obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
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aes-arm-y := aes-armv4.o aes_glue.o
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aes-arm-bs-y := aesbs-core.o aesbs-glue.o
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sha1-arm-y := sha1-armv4-large.o sha1_glue.o
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sha1-arm-neon-y := sha1-armv7-neon.o sha1_neon_glue.o
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sha512-arm-neon-y := sha512-armv7-neon.o sha512_neon_glue.o
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sha1-arm-ce-y := sha1-ce-core.o sha1-ce-glue.o
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quiet_cmd_perl = PERL $@
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cmd_perl = $(PERL) $(<) > $(@)
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134
arch/arm/crypto/sha1-ce-core.S
Normal file
134
arch/arm/crypto/sha1-ce-core.S
Normal file
@ -0,0 +1,134 @@
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/*
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* sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
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*
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.text
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.fpu crypto-neon-fp-armv8
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k0 .req q0
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k1 .req q1
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k2 .req q2
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k3 .req q3
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ta0 .req q4
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ta1 .req q5
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tb0 .req q5
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tb1 .req q4
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dga .req q6
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dgb .req q7
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dgbs .req s28
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dg0 .req q12
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dg1a0 .req q13
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dg1a1 .req q14
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dg1b0 .req q14
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dg1b1 .req q13
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.macro add_only, op, ev, rc, s0, dg1
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.ifnb \s0
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vadd.u32 tb\ev, q\s0, \rc
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.endif
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sha1h.32 dg1b\ev, dg0
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.ifb \dg1
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sha1\op\().32 dg0, dg1a\ev, ta\ev
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.else
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sha1\op\().32 dg0, \dg1, ta\ev
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.endif
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.endm
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.macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
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sha1su0.32 q\s0, q\s1, q\s2
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add_only \op, \ev, \rc, \s1, \dg1
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sha1su1.32 q\s0, q\s3
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.endm
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.align 6
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.Lsha1_rcon:
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.word 0x5a827999, 0x5a827999, 0x5a827999, 0x5a827999
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.word 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1, 0x6ed9eba1
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.word 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc, 0x8f1bbcdc
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.word 0xca62c1d6, 0xca62c1d6, 0xca62c1d6, 0xca62c1d6
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/*
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* void sha1_ce_transform(int blocks, u8 const *src, u32 *state,
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* u8 *head);
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*/
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ENTRY(sha1_ce_transform)
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/* load round constants */
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adr ip, .Lsha1_rcon
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vld1.32 {k0-k1}, [ip, :128]!
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vld1.32 {k2-k3}, [ip, :128]
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/* load state */
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vld1.32 {dga}, [r2]
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vldr dgbs, [r2, #16]
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/* load partial input (if supplied) */
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teq r3, #0
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beq 0f
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vld1.32 {q8-q9}, [r3]!
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vld1.32 {q10-q11}, [r3]
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teq r0, #0
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b 1f
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/* load input */
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0: vld1.32 {q8-q9}, [r1]!
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vld1.32 {q10-q11}, [r1]!
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subs r0, r0, #1
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1:
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#ifndef CONFIG_CPU_BIG_ENDIAN
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vrev32.8 q8, q8
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vrev32.8 q9, q9
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vrev32.8 q10, q10
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vrev32.8 q11, q11
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#endif
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vadd.u32 ta0, q8, k0
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vmov dg0, dga
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add_update c, 0, k0, 8, 9, 10, 11, dgb
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add_update c, 1, k0, 9, 10, 11, 8
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add_update c, 0, k0, 10, 11, 8, 9
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add_update c, 1, k0, 11, 8, 9, 10
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add_update c, 0, k1, 8, 9, 10, 11
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add_update p, 1, k1, 9, 10, 11, 8
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add_update p, 0, k1, 10, 11, 8, 9
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add_update p, 1, k1, 11, 8, 9, 10
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add_update p, 0, k1, 8, 9, 10, 11
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add_update p, 1, k2, 9, 10, 11, 8
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add_update m, 0, k2, 10, 11, 8, 9
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add_update m, 1, k2, 11, 8, 9, 10
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add_update m, 0, k2, 8, 9, 10, 11
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add_update m, 1, k2, 9, 10, 11, 8
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add_update m, 0, k3, 10, 11, 8, 9
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add_update p, 1, k3, 11, 8, 9, 10
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add_only p, 0, k3, 9
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add_only p, 1, k3, 10
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add_only p, 0, k3, 11
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add_only p, 1
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/* update state */
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vadd.u32 dga, dga, dg0
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vadd.u32 dgb, dgb, dg1a0
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bne 0b
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/* store new state */
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vst1.32 {dga}, [r2]
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vstr dgbs, [r2, #16]
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bx lr
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ENDPROC(sha1_ce_transform)
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150
arch/arm/crypto/sha1-ce-glue.c
Normal file
150
arch/arm/crypto/sha1-ce-glue.c
Normal file
@ -0,0 +1,150 @@
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/*
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* sha1-ce-glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions
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*
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* Copyright (C) 2015 Linaro Ltd <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <crypto/internal/hash.h>
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#include <crypto/sha.h>
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#include <linux/crypto.h>
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#include <linux/module.h>
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#include <asm/crypto/sha1.h>
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#include <asm/hwcap.h>
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#include <asm/neon.h>
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#include <asm/simd.h>
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#include <asm/unaligned.h>
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MODULE_DESCRIPTION("SHA1 secure hash using ARMv8 Crypto Extensions");
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MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
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MODULE_LICENSE("GPL v2");
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asmlinkage void sha1_ce_transform(int blocks, u8 const *src, u32 *state,
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u8 *head);
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static int sha1_init(struct shash_desc *desc)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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*sctx = (struct sha1_state){
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.state = { SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4 },
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};
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return 0;
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}
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static int sha1_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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unsigned int partial;
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if (!may_use_simd())
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return sha1_update_arm(desc, data, len);
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partial = sctx->count % SHA1_BLOCK_SIZE;
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sctx->count += len;
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if ((partial + len) >= SHA1_BLOCK_SIZE) {
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int blocks;
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if (partial) {
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int p = SHA1_BLOCK_SIZE - partial;
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memcpy(sctx->buffer + partial, data, p);
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data += p;
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len -= p;
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}
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blocks = len / SHA1_BLOCK_SIZE;
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len %= SHA1_BLOCK_SIZE;
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kernel_neon_begin();
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sha1_ce_transform(blocks, data, sctx->state,
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partial ? sctx->buffer : NULL);
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kernel_neon_end();
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data += blocks * SHA1_BLOCK_SIZE;
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partial = 0;
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}
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if (len)
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memcpy(sctx->buffer + partial, data, len);
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return 0;
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}
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static int sha1_final(struct shash_desc *desc, u8 *out)
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{
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static const u8 padding[SHA1_BLOCK_SIZE] = { 0x80, };
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struct sha1_state *sctx = shash_desc_ctx(desc);
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__be64 bits = cpu_to_be64(sctx->count << 3);
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__be32 *dst = (__be32 *)out;
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int i;
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u32 padlen = SHA1_BLOCK_SIZE
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- ((sctx->count + sizeof(bits)) % SHA1_BLOCK_SIZE);
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sha1_update(desc, padding, padlen);
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sha1_update(desc, (const u8 *)&bits, sizeof(bits));
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for (i = 0; i < SHA1_DIGEST_SIZE / sizeof(__be32); i++)
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put_unaligned_be32(sctx->state[i], dst++);
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*sctx = (struct sha1_state){};
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return 0;
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}
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static int sha1_export(struct shash_desc *desc, void *out)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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struct sha1_state *dst = out;
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*dst = *sctx;
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return 0;
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}
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static int sha1_import(struct shash_desc *desc, const void *in)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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struct sha1_state const *src = in;
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*sctx = *src;
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return 0;
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}
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static struct shash_alg alg = {
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.init = sha1_init,
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.update = sha1_update,
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.final = sha1_final,
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.export = sha1_export,
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.import = sha1_import,
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.descsize = sizeof(struct sha1_state),
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.digestsize = SHA1_DIGEST_SIZE,
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.statesize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name = "sha1-ce",
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.cra_priority = 200,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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static int __init sha1_ce_mod_init(void)
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{
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if (!(elf_hwcap2 & HWCAP2_SHA1))
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return -ENODEV;
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return crypto_register_shash(&alg);
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}
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static void __exit sha1_ce_mod_fini(void)
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{
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crypto_unregister_shash(&alg);
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}
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module_init(sha1_ce_mod_init);
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module_exit(sha1_ce_mod_fini);
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