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ASoC: wm8960: Fix PLL register writes

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Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.

Signed-off-by: Mike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
This commit is contained in:
Mike Dyer 2013-08-16 18:36:28 +01:00 committed by Mark Brown
parent d4e4ab86bc
commit 85fa532b6e
1 changed files with 3 additions and 3 deletions
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6
sound/soc/codecs/wm8960.c
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@ -857,9 +857,9 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
if (pll_div.k) {
reg |= 0x20;
snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f);
snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff);
snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff);
snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
}
snd_soc_write(codec, WM8960_PLL1, reg);