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imx-drm: match ipu_di_signal_cfg's clk_pol with its description.

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According to the datasheet, setting the di0_polarity_disp_clk
field in the GENERAL di register sets the output clock polarity
to active high.

Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Denis Carikli 2014-04-07 14:44:43 +02:00 committed by Russell King
parent c9eaa447e7
commit 85de9d17c4
2 changed files with 2 additions and 2 deletions
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2
drivers/staging/imx-drm/ipu-v3/ipu-di.c
View File

@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
}
}
if (!sig->clk_pol)
if (sig->clk_pol)
di_gen |= DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL);

2
drivers/staging/imx-drm/ipuv3-crtc.c
View File

@ -158,7 +158,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
sig_cfg.Vsync_pol = 1;
sig_cfg.enable_pol = 1;
sig_cfg.clk_pol = 1;
sig_cfg.clk_pol = 0;
sig_cfg.width = mode->hdisplay;
sig_cfg.height = mode->vdisplay;
sig_cfg.pixel_fmt = out_pixel_fmt;