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arm: tcc8k: Choose PLL settings conforming to board layout

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The evaluation board is driven with 1.2V core voltage, so system clock
must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose
appropriate values and set DTCMWAIT accordingly. Adapt UART setting to
avoid console log interruption and wait for the specified locking time
of 300us to pass.

Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Oskar Schirmer 2011-02-17 16:42:58 +01:00 committed by Thomas Gleixner
parent 30d913556b
commit 85922e54a3
1 changed files with 18 additions and 0 deletions
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18
arch/arm/mach-tcc8k/board-tcc8000-sdk.c
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@ -6,6 +6,7 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/delay.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
@ -18,6 +19,7 @@
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/tcc-nand.h> #include <mach/tcc-nand.h>
#include <mach/tcc8k-regs.h>
#include "common.h" #include "common.h"
@ -52,6 +54,22 @@ static struct sys_timer tcc8k_timer = {
static void __init tcc8k_map_io(void) static void __init tcc8k_map_io(void)
{ {
tcc8k_map_common_io(); tcc8k_map_common_io();
/* set PLL0 clock to 96MHz, adapt UART0 divisor */
__raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS);
__raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS);
/* set PLL1 clock to 192MHz */
__raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS);
/* set PLL2 clock to 48MHz */
__raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS);
/* with CPU freq higher than 150 MHz, need extra DTCM wait */
__raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS);
/* PLL locking time as specified */
udelay(300);
} }
MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")