mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-22 20:23:57 +08:00
ARM: 6381/1: Use lazy cache flushing on ARMv7 SMP systems
ARMv7 processors like Cortex-A9 broadcast the cache maintenance operations in hardware. This patch allows the flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode similar to the UP case. Note that cache flushing on SMP systems now takes place via the set_pte_at() call (__sync_icache_dcache) and there is no race with other CPUs executing code from the new PTE before the cache flushing took place. Tested-by: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
parent
6012191aa9
commit
85848dd7ab
arch/arm
@ -13,9 +13,13 @@ static inline int tlb_ops_need_broadcast(void)
|
||||
return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
|
||||
#define cache_ops_need_broadcast() 0
|
||||
#else
|
||||
static inline int cache_ops_need_broadcast(void)
|
||||
{
|
||||
return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
@ -17,6 +17,7 @@
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include "mm.h"
|
||||
|
||||
@ -93,12 +94,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
|
||||
#define flush_pfn_alias(pfn,vaddr) do { } while (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static void flush_ptrace_access_other(void *args)
|
||||
{
|
||||
__flush_icache_all();
|
||||
}
|
||||
#endif
|
||||
|
||||
static
|
||||
void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
||||
@ -122,11 +121,9 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
|
||||
if (vma->vm_flags & VM_EXEC) {
|
||||
unsigned long addr = (unsigned long)kaddr;
|
||||
__cpuc_coherent_kern_range(addr, addr + len);
|
||||
#ifdef CONFIG_SMP
|
||||
if (cache_ops_need_broadcast())
|
||||
smp_call_function(flush_ptrace_access_other,
|
||||
NULL, 1);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
@ -276,12 +273,10 @@ void flush_dcache_page(struct page *page)
|
||||
|
||||
mapping = page_mapping(page);
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
if (mapping && !mapping_mapped(mapping))
|
||||
if (!cache_ops_need_broadcast() &&
|
||||
mapping && !mapping_mapped(mapping))
|
||||
clear_bit(PG_dcache_clean, &page->flags);
|
||||
else
|
||||
#endif
|
||||
{
|
||||
else {
|
||||
__flush_dcache_page(mapping, page);
|
||||
if (mapping && cache_is_vivt())
|
||||
__flush_dcache_aliases(mapping, page);
|
||||
|
Loading…
Reference in New Issue
Block a user