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ARM: LPC32xx: Add the motor PWM clock
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@ -585,6 +585,13 @@ static struct clk clk_timer3 = {
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.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
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.get_rate = local_return_parent_rate,
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};
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static struct clk clk_mpwm = {
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.parent = &clk_pclk,
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.enable = local_onoff_enable,
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.enable_reg = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
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.enable_mask = LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN,
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.get_rate = local_return_parent_rate,
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};
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static struct clk clk_wdt = {
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.parent = &clk_pclk,
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.enable = local_onoff_enable,
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@ -1202,6 +1209,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
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CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
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CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
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CLKDEV_INIT("400e8000.mpwm", NULL, &clk_mpwm),
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CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
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CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
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CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
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@ -515,6 +515,7 @@
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/*
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* clkpwr_timers_pwms_clk_ctrl_1 register definitions
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*/
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#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40
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#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
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#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
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#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
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