mirror of
https://github.com/edk2-porting/linux-next.git
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Quite a lot changes but it looks like DT approach is really paying off.
BG2Q joins Berlin SoC family with corresponding development board, DW gpio nodes for all SoCs. Most notably, we have settled clock bindings to allow us to continue on drivers requiring clocks and pinctrl bindings. Last but not least, BG2Q gained SDHCI support and is able to properly boot into userspace. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTenGqAAoJEN2kpao7fSL4TzgP/0lTj/kMs6jMvJ/Jq92PhJAX sdyCC5sWdJuC88RcteOaQ5VlGF9bGj9J2RNBDmnyC+HqYbc+e1fmQW+U/+rmcMBt T5OdmrVY9UxyfpVuXlUN2Y3MORiKNoxZyr8L9GoaER5FrUYQwgGbi+8HyEh3RMV+ np6TJ+zYDpSTZHJmBSvn1xzwVKtDXPDi8kbteFjV4VjUOKJjrWRCSi5Tu71J3C2D yljmLZZR2Ei96+6YrgyL4qeQkATN3VpAzVDs2jl7SmAK7oRHW1mkBr3ToZQ8cc56 gWUuyeOOU8vSXk+bkp0bIPDxFqfy9LBJqxfG0wVcbWN51as/MmqoorWgU6MQXVHV Oe292vEi1c+zgsGS4Qg2G0aeIV5ORATa79eHaw4IYM6YXKMoNAI+JFt46SvA0QY7 xKlnjwhgRhN1K5G+veJyemi+L/1KwjPqNbfHpFibmaQV/Q5pNtON2WR93LgUO42Q 3daOH7nSHatCo81iSzy8NoQD1rgylFq8HOFGFdfp+QL68qLb7wsn6goOtcltWYBE TT7C/YyjWdy13MQaJkrRZQIKPMDGFk6X3Bd6yWICbiPZW9svBkM9cFeqiyJo0CEu miHIVMxgoOVt1LyC08w9A66fhFuKrWI0Si6Ig573klvpzUBfy9lc2KcZ+stheCkZ 6VW13d+DfBoyy+z78rQ/ =C9FR -----END PGP SIGNATURE----- Merge tag 'berlin-dt-3.16' of https://github.com/shesselba/linux-berlin into next/dt Merge "ARM: berlin: DT changes for v3.16" from Sebastian Hesselbart: Quite a lot changes but it looks like DT approach is really paying off. BG2Q joins Berlin SoC family with corresponding development board, DW gpio nodes for all SoCs. Most notably, we have settled clock bindings to allow us to continue on drivers requiring clocks and pinctrl bindings. Last but not least, BG2Q gained SDHCI support and is able to properly boot into userspace. * tag 'berlin-dt-3.16' of https://github.com/shesselba/linux-berlin: ARM: dts: berlin: enable SD card reader and eMMC for the BG2Q DMP ARM: dts: berlin: add the SDHCI nodes for the BG2Q ARM: dts: berlin: add the pinctrl node and muxing setup for uarts dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs ARM: dts: berlin: convert BG2Q to DT clock nodes ARM: dts: berlin: convert BG2 to DT clock nodes ARM: dts: berlin: convert BG2CD to DT clock nodes clk: berlin: add binding include for Berlin SoC clock ids dt-binding: ARM: add clock binding docs for Marvell Berlin2 SoCs ARM: dts: berlin: add the BG2CD GPIO nodes ARM: dts: berlin: add the BG2 GPIO nodes ARM: dts: berlin: add the BG2Q GPIO nodes ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q ARM: dts: berlin: add the Marvell BG2-Q DMP device tree ARM: dts: berlin: add the Marvell Armada 1500 pro Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
84cc8a7114
@ -12,6 +12,7 @@ SoC and board used. Currently known SoC compatibles are:
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"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
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"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
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"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
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"marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
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"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
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* Example:
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@ -22,3 +23,104 @@ SoC and board used. Currently known SoC compatibles are:
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...
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}
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* Marvell Berlin2 chip control binding
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Marvell Berlin SoCs have a chip control register set providing several
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individual registers dealing with pinmux, padmux, clock, reset, and secondary
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CPU boot address. Unfortunately, the individual registers are spread among the
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chip control registers, so there should be a single DT node only providing the
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different functions which are described below.
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Required properties:
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- compatible: shall be one of
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"marvell,berlin2-chip-ctrl" for BG2
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"marvell,berlin2cd-chip-ctrl" for BG2CD
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"marvell,berlin2q-chip-ctrl" for BG2Q
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- reg: address and length of following register sets for
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BG2/BG2CD: chip control register set
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BG2Q: chip control register set and cpu pll registers
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* Marvell Berlin2 system control binding
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Marvell Berlin SoCs have a system control register set providing several
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individual registers dealing with pinmux, padmux, and reset.
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Required properties:
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- compatible: should be one of
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"marvell,berlin2-system-ctrl" for BG2
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"marvell,berlin2cd-system-ctrl" for BG2CD
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"marvell,berlin2q-system-ctrl" for BG2Q
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- reg: address and length of the system control register set
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* Clock provider binding
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As clock related registers are spread among the chip control registers, the
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chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
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SoCs share the same IP for PLLs and clocks, with some minor differences in
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features and register layout.
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Required properties:
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- #clock-cells: shall be set to 1
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- clocks: clock specifiers referencing the core clock input clocks
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- clock-names: array of strings describing the input clock specifiers above.
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Allowed clock-names for the reference clocks are
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"refclk" for the SoCs osciallator input on all SoCs,
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and SoC-specific input clocks for
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BG2/BG2CD: "video_ext0" for the external video clock input
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Clocks provided by core clocks shall be referenced by a clock specifier
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indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
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for the corresponding index mapping.
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* Pin controller binding
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Pin control registers are part of both register sets, chip control and system
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control. The pins controlled are organized in groups, so no actual pin
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information is needed.
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A pin-controller node should contain subnodes representing the pin group
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configurations, one per function. Each subnode has the group name and the muxing
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function used.
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Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
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a 'function' in the pin-controller subsystem.
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Required subnode-properties:
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- groups: a list of strings describing the group names.
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- function: a string describing the function used to mux the groups.
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Example:
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chip: chip-control@ea0000 {
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compatible = "marvell,berlin2-chip-ctrl";
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#clock-cells = <1>;
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reg = <0xea0000 0x400>;
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clocks = <&refclk>, <&externaldev 0>;
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clock-names = "refclk", "video_ext0";
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spi1_pmux: spi1-pmux {
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groups = "G0";
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function = "spi1";
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};
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};
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sysctrl: system-controller@d000 {
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compatible = "marvell,berlin2-system-ctrl";
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reg = <0xd000 0x100>;
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uart0_pmux: uart0-pmux {
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groups = "GSM4";
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function = "uart0";
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};
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uart1_pmux: uart1-pmux {
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groups = "GSM5";
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function = "uart1";
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};
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uart2_pmux: uart2-pmux {
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groups = "GSM3";
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function = "uart2";
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};
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};
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@ -56,7 +56,8 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
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bcm21664-garnet.dtb
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dtb-$(CONFIG_ARCH_BERLIN) += \
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berlin2-sony-nsz-gs7.dtb \
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berlin2cd-google-chromecast.dtb
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berlin2cd-google-chromecast.dtb \
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berlin2q-marvell-dmp.dtb
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dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
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da850-evm.dtb
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dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
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@ -12,6 +12,7 @@
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/berlin2.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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@ -37,24 +38,10 @@
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};
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};
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clocks {
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smclk: sysmgr-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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cfgclk: cfg-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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};
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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soc {
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@ -72,6 +59,11 @@
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cache-level = <2>;
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};
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scu: snoop-control-unit@ad0000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xad0000 0x58>;
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};
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gic: interrupt-controller@ad1000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
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@ -83,7 +75,7 @@
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xad0600 0x20>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysclk>;
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clocks = <&chip CLKID_TWD>;
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};
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apb@e80000 {
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@ -94,11 +86,83 @@
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ranges = <0 0xe80000 0x10000>;
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interrupt-parent = <&aic>;
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gpio0: gpio@0400 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0400 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-port@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0>;
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};
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};
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gpio1: gpio@0800 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0800 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-port@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <1>;
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};
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};
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gpio2: gpio@0c00 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x0c00 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-port@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <2>;
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};
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};
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gpio3: gpio@1000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x1000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-port@3 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <3>;
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};
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};
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timer0: timer@2c00 {
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compatible = "snps,dw-apb-timer";
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reg = <0x2c00 0x14>;
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interrupts = <8>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "okay";
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};
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@ -107,7 +171,7 @@
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compatible = "snps,dw-apb-timer";
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reg = <0x2c14 0x14>;
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interrupts = <9>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "okay";
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};
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@ -116,7 +180,7 @@
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compatible = "snps,dw-apb-timer";
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reg = <0x2c28 0x14>;
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interrupts = <10>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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@ -125,7 +189,7 @@
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compatible = "snps,dw-apb-timer";
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reg = <0x2c3c 0x14>;
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interrupts = <11>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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@ -134,7 +198,7 @@
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compatible = "snps,dw-apb-timer";
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reg = <0x2c50 0x14>;
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interrupts = <12>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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@ -143,7 +207,7 @@
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compatible = "snps,dw-apb-timer";
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reg = <0x2c64 0x14>;
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interrupts = <13>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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@ -152,7 +216,7 @@
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compatible = "snps,dw-apb-timer";
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reg = <0x2c78 0x14>;
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interrupts = <14>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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@ -161,7 +225,7 @@
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compatible = "snps,dw-apb-timer";
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reg = <0x2c8c 0x14>;
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interrupts = <15>;
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clocks = <&cfgclk>;
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clocks = <&chip CLKID_CFG>;
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clock-names = "timer";
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status = "disabled";
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};
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@ -176,6 +240,14 @@
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};
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};
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chip: chip-control@ea0000 {
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compatible = "marvell,berlin2-chip-ctrl";
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#clock-cells = <1>;
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reg = <0xea0000 0x400>;
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clocks = <&refclk>;
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clock-names = "refclk";
|
||||
};
|
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|
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apb@fc0000 {
|
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compatible = "simple-bus";
|
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#address-cells = <1>;
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@ -184,13 +256,48 @@
|
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ranges = <0 0xfc0000 0x10000>;
|
||||
interrupt-parent = <&sic>;
|
||||
|
||||
sm_gpio1: gpio@5000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x5000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-port@5 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sm_gpio0: gpio@c000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xc000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-port@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <11>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@9000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
interrupts = <8>;
|
||||
clocks = <&smclk>;
|
||||
clocks = <&refclk>;
|
||||
pinctrl-0 = <&uart0_pmux>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -200,7 +307,9 @@
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
interrupts = <9>;
|
||||
clocks = <&smclk>;
|
||||
clocks = <&refclk>;
|
||||
pinctrl-0 = <&uart1_pmux>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -210,10 +319,32 @@
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
interrupts = <10>;
|
||||
clocks = <&smclk>;
|
||||
clocks = <&refclk>;
|
||||
pinctrl-0 = <&uart2_pmux>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sysctrl: system-controller@d000 {
|
||||
compatible = "marvell,berlin2-system-ctrl";
|
||||
reg = <0xd000 0x100>;
|
||||
|
||||
uart0_pmux: uart0-pmux {
|
||||
groups = "GSM4";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
uart1_pmux: uart1-pmux {
|
||||
groups = "GSM5";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
uart2_pmux: uart2-pmux {
|
||||
groups = "GSM3";
|
||||
function = "uart2";
|
||||
};
|
||||
};
|
||||
|
||||
sic: interrupt-controller@e000 {
|
||||
compatible = "snps,dw-apb-ictl";
|
||||
reg = <0xe000 0x400>;
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/clock/berlin2.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
@ -30,24 +31,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
smclk: sysmgr-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
cfgclk: cfg-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <75000000>;
|
||||
};
|
||||
|
||||
sysclk: system-clock {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <300000000>;
|
||||
};
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
@ -76,7 +63,7 @@
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xad0600 0x20>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sysclk>;
|
||||
clocks = <&chip CLKID_TWD>;
|
||||
};
|
||||
|
||||
apb@e80000 {
|
||||
@ -87,11 +74,83 @@
|
||||
ranges = <0 0xe80000 0x10000>;
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
gpio0: gpio@0400 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0400 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-port@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@0800 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-port@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@0c00 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0c00 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-port@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@1000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x1000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-port@3 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer0: timer@2c00 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c00 0x14>;
|
||||
interrupts = <8>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "okay";
|
||||
};
|
||||
@ -100,7 +159,7 @@
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c14 0x14>;
|
||||
interrupts = <9>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "okay";
|
||||
};
|
||||
@ -109,7 +168,7 @@
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c28 0x14>;
|
||||
interrupts = <10>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -118,7 +177,7 @@
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c3c 0x14>;
|
||||
interrupts = <11>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -127,7 +186,7 @@
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c50 0x14>;
|
||||
interrupts = <12>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -136,7 +195,7 @@
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c64 0x14>;
|
||||
interrupts = <13>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -145,7 +204,7 @@
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c78 0x14>;
|
||||
interrupts = <14>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -154,7 +213,7 @@
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c8c 0x14>;
|
||||
interrupts = <15>;
|
||||
clocks = <&cfgclk>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -169,6 +228,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
chip: chip-control@ea0000 {
|
||||
compatible = "marvell,berlin2cd-chip-ctrl";
|
||||
#clock-cells = <1>;
|
||||
reg = <0xea0000 0x400>;
|
||||
clocks = <&refclk>;
|
||||
clock-names = "refclk";
|
||||
|
||||
uart0_pmux: uart0-pmux {
|
||||
groups = "G6";
|
||||
function = "uart0";
|
||||
};
|
||||
};
|
||||
|
||||
apb@fc0000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -177,13 +249,45 @@
|
||||
ranges = <0 0xfc0000 0x10000>;
|
||||
interrupt-parent = <&sic>;
|
||||
|
||||
sm_gpio1: gpio@5000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x5000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-port@5 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sm_gpio0: gpio@c000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xc000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-port@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <8>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@9000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
interrupts = <8>;
|
||||
clocks = <&smclk>;
|
||||
clocks = <&refclk>;
|
||||
pinctrl-0 = <&uart0_pmux>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -193,10 +297,15 @@
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
interrupts = <9>;
|
||||
clocks = <&smclk>;
|
||||
clocks = <&refclk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sysctrl: system-controller@d000 {
|
||||
compatible = "marvell,berlin2cd-system-ctrl";
|
||||
reg = <0xd000 0x100>;
|
||||
};
|
||||
|
||||
sic: interrupt-controller@e000 {
|
||||
compatible = "snps,dw-apb-ictl";
|
||||
reg = <0xe000 0x400>;
|
||||
|
||||
39
arch/arm/boot/dts/berlin2q-marvell-dmp.dts
Normal file
39
arch/arm/boot/dts/berlin2q-marvell-dmp.dts
Normal file
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "berlin2q.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell BG2-Q DMP";
|
||||
compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>;
|
||||
};
|
||||
|
||||
choosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
broken-cd;
|
||||
sdhci,wp-inverted;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci2 {
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
363
arch/arm/boot/dts/berlin2q.dtsi
Normal file
363
arch/arm/boot/dts/berlin2q.dtsi
Normal file
@ -0,0 +1,363 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/berlin2q.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 1500 pro (BG2-Q) SoC";
|
||||
compatible = "marvell,berlin2q", "marvell,berlin";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&l2>;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0xf7000000 0x1000000>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
sdhci0: sdhci@ab0000 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xab0000 0x200>;
|
||||
clocks = <&chip CLKID_SDIO1XIN>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci1: sdhci@ab0800 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xab0800 0x200>;
|
||||
clocks = <&chip CLKID_SDIO1XIN>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci2: sdhci@ab1000 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xab1000 0x200>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&chip CLKID_SDIO1XIN>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
l2: l2-cache-controller@ac0000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xac0000 0x1000>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
scu: snoop-control-unit@ad0000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xad0000 0x58>;
|
||||
};
|
||||
|
||||
local-timer@ad0600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xad0600 0x20>;
|
||||
clocks = <&chip CLKID_TWD>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@ad1000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0xad1000 0x1000>, <0xad0100 0x100>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
apb@e80000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0xe80000 0x10000>;
|
||||
interrupt-parent = <&aic>;
|
||||
|
||||
gpio0: gpio@0400 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0400 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porta: gpio-port@0 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio1: gpio@0800 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portb: gpio-port@1 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@0c00 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x0c00 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portc: gpio-port@2 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio3: gpio@1000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x1000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portd: gpio-port@3 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer0: timer@2c00 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c00 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
interrupts = <8>;
|
||||
};
|
||||
|
||||
timer1: timer@2c14 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c14 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer2: timer@2c28 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c28 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer3: timer@2c3c {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c3c 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer4: timer@2c50 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c50 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer5: timer@2c64 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c64 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer6: timer@2c78 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c78 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer7: timer@2c8c {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
reg = <0x2c8c 0x14>;
|
||||
clocks = <&chip CLKID_CFG>;
|
||||
clock-names = "timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aic: interrupt-controller@3800 {
|
||||
compatible = "snps,dw-apb-ictl";
|
||||
reg = <0x3800 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio4: gpio@5000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0x5000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
porte: gpio-port@4 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio5: gpio@c000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xc000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
portf: gpio-port@5 {
|
||||
compatible = "snps,dw-apb-gpio-port";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
snps,nr-gpios = <32>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
chip: chip-control@ea0000 {
|
||||
compatible = "marvell,berlin2q-chip-ctrl";
|
||||
#clock-cells = <1>;
|
||||
reg = <0xea0000 0x400>, <0xdd0170 0x10>;
|
||||
clocks = <&refclk>;
|
||||
clock-names = "refclk";
|
||||
};
|
||||
|
||||
apb@fc0000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0 0xfc0000 0x10000>;
|
||||
interrupt-parent = <&sic>;
|
||||
|
||||
uart0: uart@9000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x9000 0x100>;
|
||||
interrupt-parent = <&sic>;
|
||||
interrupts = <8>;
|
||||
clocks = <&refclk>;
|
||||
reg-shift = <2>;
|
||||
pinctrl-0 = <&uart0_pmux>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: uart@a000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xa000 0x100>;
|
||||
interrupt-parent = <&sic>;
|
||||
interrupts = <9>;
|
||||
clocks = <&refclk>;
|
||||
reg-shift = <2>;
|
||||
pinctrl-0 = <&uart1_pmux>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sysctrl: pin-controller@d000 {
|
||||
compatible = "marvell,berlin2q-system-ctrl";
|
||||
reg = <0xd000 0x100>;
|
||||
|
||||
uart0_pmux: uart0-pmux {
|
||||
groups = "GSM12";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
uart1_pmux: uart1-pmux {
|
||||
groups = "GSM14";
|
||||
function = "uart1";
|
||||
};
|
||||
};
|
||||
|
||||
sic: interrupt-controller@e000 {
|
||||
compatible = "snps,dw-apb-ictl";
|
||||
reg = <0xe000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
45
include/dt-bindings/clock/berlin2.h
Normal file
45
include/dt-bindings/clock/berlin2.h
Normal file
@ -0,0 +1,45 @@
|
||||
/*
|
||||
* Berlin2 BG2/BG2CD clock tree IDs
|
||||
*/
|
||||
|
||||
#define CLKID_SYS 0
|
||||
#define CLKID_CPU 1
|
||||
#define CLKID_DRMFIGO 2
|
||||
#define CLKID_CFG 3
|
||||
#define CLKID_GFX 4
|
||||
#define CLKID_ZSP 5
|
||||
#define CLKID_PERIF 6
|
||||
#define CLKID_PCUBE 7
|
||||
#define CLKID_VSCOPE 8
|
||||
#define CLKID_NFC_ECC 9
|
||||
#define CLKID_VPP 10
|
||||
#define CLKID_APP 11
|
||||
#define CLKID_AUDIO0 12
|
||||
#define CLKID_AUDIO2 13
|
||||
#define CLKID_AUDIO3 14
|
||||
#define CLKID_AUDIO1 15
|
||||
#define CLKID_GFX3D_CORE 16
|
||||
#define CLKID_GFX3D_SYS 17
|
||||
#define CLKID_ARC 18
|
||||
#define CLKID_VIP 19
|
||||
#define CLKID_SDIO0XIN 20
|
||||
#define CLKID_SDIO1XIN 21
|
||||
#define CLKID_GFX3D_EXTRA 22
|
||||
#define CLKID_GC360 23
|
||||
#define CLKID_SDIO_DLLMST 24
|
||||
#define CLKID_GETH0 25
|
||||
#define CLKID_GETH1 26
|
||||
#define CLKID_SATA 27
|
||||
#define CLKID_AHBAPB 28
|
||||
#define CLKID_USB0 29
|
||||
#define CLKID_USB1 30
|
||||
#define CLKID_PBRIDGE 31
|
||||
#define CLKID_SDIO0 32
|
||||
#define CLKID_SDIO1 33
|
||||
#define CLKID_NFC 34
|
||||
#define CLKID_SMEMC 35
|
||||
#define CLKID_AUDIOHD 36
|
||||
#define CLKID_VIDEO0 37
|
||||
#define CLKID_VIDEO1 38
|
||||
#define CLKID_VIDEO2 39
|
||||
#define CLKID_TWD 40
|
||||
31
include/dt-bindings/clock/berlin2q.h
Normal file
31
include/dt-bindings/clock/berlin2q.h
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Berlin2 BG2Q clock tree IDs
|
||||
*/
|
||||
|
||||
#define CLKID_SYS 0
|
||||
#define CLKID_DRMFIGO 1
|
||||
#define CLKID_CFG 2
|
||||
#define CLKID_GFX2D 3
|
||||
#define CLKID_ZSP 4
|
||||
#define CLKID_PERIF 5
|
||||
#define CLKID_PCUBE 6
|
||||
#define CLKID_VSCOPE 7
|
||||
#define CLKID_NFC_ECC 8
|
||||
#define CLKID_VPP 9
|
||||
#define CLKID_APP 10
|
||||
#define CLKID_SDIO0XIN 11
|
||||
#define CLKID_SDIO1XIN 12
|
||||
#define CLKID_GFX2DAXI 13
|
||||
#define CLKID_GETH0 14
|
||||
#define CLKID_SATA 15
|
||||
#define CLKID_AHBAPB 16
|
||||
#define CLKID_USB0 17
|
||||
#define CLKID_USB1 18
|
||||
#define CLKID_USB2 19
|
||||
#define CLKID_USB3 20
|
||||
#define CLKID_PBRIDGE 21
|
||||
#define CLKID_SDIO 22
|
||||
#define CLKID_NFC 23
|
||||
#define CLKID_SMEMC 24
|
||||
#define CLKID_PCIE 25
|
||||
#define CLKID_TWD 26
|
||||
Loading…
Reference in New Issue
Block a user