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PCI: mvebu: Adapt to the new device tree layout
The new device tree layout encodes the window's target ID and attribute in the PCIe controller node's ranges property. This allows to parse such entries to obtain such information and use the recently introduced MBus API to create the windows, instead of using the current name based scheme. Cc: devicetree@vger.kernel.org Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Thomas Petazzoni
Jason Cooper
parent
0b1252784b
commit
84384a4504
@ -1,6 +1,7 @@
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* Marvell EBU PCIe interfaces
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Mandatory properties:
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- compatible: one of the following values:
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marvell,armada-370-pcie
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marvell,armada-xp-pcie
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@ -10,11 +11,49 @@ Mandatory properties:
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- #interrupt-cells, set to <1>
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- bus-range: PCI bus numbers covered
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- device_type, set to "pci"
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- ranges: ranges for the PCI memory and I/O regions, as well as the
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MMIO registers to control the PCIe interfaces.
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- ranges: ranges describing the MMIO registers to control the PCIe
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interfaces, and ranges describing the MBus windows needed to access
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the memory and I/O regions of each PCIe interface.
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In addition, the Device Tree node must have sub-nodes describing each
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The ranges describing the MMIO registers have the following layout:
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0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
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where:
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* r is a 32-bits value that gives the offset of the MMIO
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registers of this PCIe interface, from the base of the internal
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registers.
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* s is a 32-bits value that give the size of this MMIO
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registers area. This range entry translates the '0x82000000 0 r' PCI
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address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
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of the internal register window (as identified by MBUS_ID(0xf0,
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0x01)).
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The ranges describing the MBus windows have the following layout:
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0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
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where:
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* t is the type of the MBus window (as defined by the standard PCI DT
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bindings), 1 for I/O and 2 for memory.
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* s is the PCI slot that corresponds to this PCIe interface
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* w is the 'target ID' value for the MBus window
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* a the 'attribute' value for the MBus window.
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Since the location and size of the different MBus windows is not fixed in
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hardware, and only determined in runtime, those ranges cover the full first
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4 GB of the physical address space, and do not translate into a valid CPU
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address.
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In addition, the device tree node must have sub-nodes describing each
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PCIe interface, having the following mandatory properties:
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- reg: used only for interrupt mapping, so only the first four bytes
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are used to refer to the correct bus number and device number.
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- assigned-addresses: reference to the MMIO registers used to control
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@ -26,7 +65,8 @@ PCIe interface, having the following mandatory properties:
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- #address-cells, set to <3>
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- #size-cells, set to <2>
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- #interrupt-cells, set to <1>
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- ranges, empty property.
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- ranges, translating the MBus windows ranges of the parent node into
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standard PCI addresses.
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- interrupt-map-mask and interrupt-map, standard PCI properties to
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define the mapping of the PCIe interface to interrupt numbers.
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@ -47,27 +87,50 @@ pcie-controller {
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
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0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
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0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
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0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
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0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
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0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
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0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
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0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
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0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
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0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
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0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
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0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
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0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
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0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
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0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
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0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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@ -78,12 +141,13 @@ pcie-controller {
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
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assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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@ -94,12 +158,13 @@ pcie-controller {
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
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assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 60>;
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marvell,pcie-port = <0>;
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@ -110,12 +175,13 @@ pcie-controller {
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pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
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assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
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0x81000000 0 0 0x81000000 0x4 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 61>;
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marvell,pcie-port = <0>;
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@ -126,12 +192,13 @@ pcie-controller {
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pcie@5,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x2800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
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0x81000000 0 0 0x81000000 0x5 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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@ -142,12 +209,13 @@ pcie-controller {
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pcie@6,0 {
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device_type = "pci";
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assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
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assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
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reg = <0x3000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
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0x81000000 0 0 0x81000000 0x6 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 63>;
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marvell,pcie-port = <1>;
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@ -158,12 +226,13 @@ pcie-controller {
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pcie@7,0 {
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device_type = "pci";
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assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
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assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
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reg = <0x3800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
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0x81000000 0 0 0x81000000 0x7 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 64>;
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marvell,pcie-port = <1>;
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@ -174,12 +243,13 @@ pcie-controller {
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pcie@8,0 {
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device_type = "pci";
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assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
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assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
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reg = <0x4000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
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0x81000000 0 0 0x81000000 0x8 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 65>;
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marvell,pcie-port = <1>;
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@ -187,14 +257,16 @@ pcie-controller {
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clocks = <&gateclk 12>;
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status = "disabled";
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};
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pcie@9,0 {
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device_type = "pci";
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assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
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assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
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reg = <0x4800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
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0x81000000 0 0 0x81000000 0x9 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 99>;
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marvell,pcie-port = <2>;
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@ -205,12 +277,13 @@ pcie-controller {
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pcie@10,0 {
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device_type = "pci";
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assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
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assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
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reg = <0x5000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
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0x81000000 0 0 0x81000000 0xa 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 103>;
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marvell,pcie-port = <3>;
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