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IB/mlx5: Block MR WR if UMR is not possible
Check conditions that are mandatory to post_send UMR WQEs.
1. Modifying page size.
2. Modifying remote atomic permissions if atomic access is required.
If either condition is not fulfilled then fail to post_send() flow.
Fixes: c8d75a980f
("IB/mlx5: Respect new UMR capabilities")
Signed-off-by: Moni Shoua <monis@mellanox.com>
Reviewed-by: Guy Levi <guyle@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Link: https://lore.kernel.org/r/20190815083834.9245-9-leon@kernel.org
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
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25a4517214
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@ -4162,7 +4162,7 @@ static u64 get_xlt_octo(u64 bytes)
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MLX5_IB_UMR_OCTOWORD;
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}
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static __be64 frwr_mkey_mask(void)
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static __be64 frwr_mkey_mask(bool atomic)
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{
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u64 result;
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@ -4175,10 +4175,12 @@ static __be64 frwr_mkey_mask(void)
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MLX5_MKEY_MASK_LW |
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MLX5_MKEY_MASK_RR |
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MLX5_MKEY_MASK_RW |
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MLX5_MKEY_MASK_A |
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MLX5_MKEY_MASK_SMALL_FENCE |
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MLX5_MKEY_MASK_FREE;
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if (atomic)
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result |= MLX5_MKEY_MASK_A;
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return cpu_to_be64(result);
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}
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@ -4204,7 +4206,7 @@ static __be64 sig_mkey_mask(void)
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}
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static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
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struct mlx5_ib_mr *mr, u8 flags)
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struct mlx5_ib_mr *mr, u8 flags, bool atomic)
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{
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int size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
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@ -4212,7 +4214,7 @@ static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
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umr->flags = flags;
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umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
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umr->mkey_mask = frwr_mkey_mask();
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umr->mkey_mask = frwr_mkey_mask(atomic);
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}
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static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
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@ -4811,10 +4813,22 @@ static int set_reg_wr(struct mlx5_ib_qp *qp,
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{
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struct mlx5_ib_mr *mr = to_mmr(wr->mr);
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struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
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struct mlx5_ib_dev *dev = to_mdev(pd->ibpd.device);
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int mr_list_size = (mr->ndescs + mr->meta_ndescs) * mr->desc_size;
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bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
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bool atomic = wr->access & IB_ACCESS_REMOTE_ATOMIC;
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u8 flags = 0;
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if (!mlx5_ib_can_use_umr(dev, atomic)) {
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mlx5_ib_warn(to_mdev(qp->ibqp.device),
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"Fast update of %s for MR is disabled\n",
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(MLX5_CAP_GEN(dev->mdev,
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umr_modify_entity_size_disabled)) ?
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"entity size" :
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"atomic access");
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return -EINVAL;
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}
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if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
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mlx5_ib_warn(to_mdev(qp->ibqp.device),
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"Invalid IB_SEND_INLINE send flag\n");
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@ -4826,7 +4840,7 @@ static int set_reg_wr(struct mlx5_ib_qp *qp,
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if (umr_inline)
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flags |= MLX5_UMR_INLINE;
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set_reg_umr_seg(*seg, mr, flags);
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set_reg_umr_seg(*seg, mr, flags, atomic);
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*seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
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*size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
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handle_post_send_edge(&qp->sq, seg, *size, cur_edge);
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