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usb: dwc2: gadget: Final fixes for BDMA ISOC
Done fixes and tested hsotg gadget's BDMA mode. Tested Control, Bulk, Isoc, Inter transfers. Added code for isoc transfers, removed unusable code, done minor fixes. Affected functions and IRQ handlers: - dwc2_hsotg_start_req(), - dwc2_hsotg_ep_enable(), - dwc2_hsotg_ep_queue(), - dwc2_hsotg_handle_outdone(), - GINTSTS_GOUTNAKEFF handler, Removed 'has_correct_parity' flag from 'dwc2_hsotg_ep' struct. Before this patch series, to set the data pid the DWC2 gadget driver was toggling the even/odd until it match, then were leaving it set. But now I have added mechanism to set pid and excluded all code where this flag was set. Tested-by: John Keeping <john@metanate.com> Signed-off-by: Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
Vardan Mikayelyan
Felipe Balbi
parent
bd9971f0a1
commit
837e9f00bf
@ -215,7 +215,6 @@ struct dwc2_hsotg_ep {
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unsigned int periodic:1;
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unsigned int isochronous:1;
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unsigned int send_zlp:1;
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unsigned int has_correct_parity:1;
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unsigned int target_frame;
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#define TARGET_FRAME_INITIAL 0xFFFFFFFF
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bool frame_overrun;
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@ -667,6 +667,16 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
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__func__, &ureq->dma, dma_reg);
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}
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if (hs_ep->isochronous && hs_ep->interval == 1) {
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hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
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dwc2_gadget_incr_frame_num(hs_ep);
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if (hs_ep->target_frame & 0x1)
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ctrl |= DXEPCTL_SETODDFR;
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else
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ctrl |= DXEPCTL_SETEVENFR;
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}
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ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
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dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
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@ -863,9 +873,18 @@ static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
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first = list_empty(&hs_ep->queue);
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list_add_tail(&hs_req->queue, &hs_ep->queue);
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if (first)
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dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
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if (first) {
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if (!hs_ep->isochronous) {
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dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
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return 0;
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}
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while (dwc2_gadget_target_frame_elapsed(hs_ep))
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dwc2_gadget_incr_frame_num(hs_ep);
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if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
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dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
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}
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return 0;
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}
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@ -1673,9 +1692,10 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
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* adjust the ISOC parity here.
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*/
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if (!using_dma(hsotg)) {
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hs_ep->has_correct_parity = 1;
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if (hs_ep->isochronous && hs_ep->interval == 1)
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dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
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else if (hs_ep->isochronous && hs_ep->interval > 1)
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dwc2_gadget_incr_frame_num(hs_ep);
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}
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dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
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@ -2216,11 +2236,10 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
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if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
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ints &= ~DXEPINT_XFERCOMPL;
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if (ints & DXEPINT_XFERCOMPL) {
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hs_ep->has_correct_parity = 1;
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if (hs_ep->isochronous && hs_ep->interval == 1)
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dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
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if (ints & DXEPINT_STSPHSERCVD)
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dev_dbg(hsotg->dev, "%s: StsPhseRcvd asserted\n", __func__);
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if (ints & DXEPINT_XFERCOMPL) {
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dev_dbg(hsotg->dev,
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"%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
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__func__, dwc2_readl(hsotg->regs + epctl_reg),
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@ -2231,7 +2250,12 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
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* at completing IN requests here
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*/
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if (dir_in) {
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if (hs_ep->isochronous && hs_ep->interval > 1)
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dwc2_gadget_incr_frame_num(hs_ep);
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dwc2_hsotg_complete_in(hsotg, hs_ep);
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if (ints & DXEPINT_NAKINTRPT)
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ints &= ~DXEPINT_NAKINTRPT;
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if (idx == 0 && !hs_ep->req)
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dwc2_hsotg_enqueue_setup(hsotg);
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@ -2240,6 +2264,8 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
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* We're using DMA, we need to fire an OutDone here
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* as we ignore the RXFIFO.
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*/
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if (hs_ep->isochronous && hs_ep->interval > 1)
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dwc2_gadget_incr_frame_num(hs_ep);
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dwc2_hsotg_handle_outdone(hsotg, idx);
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}
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@ -2556,18 +2582,16 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
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dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
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DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
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DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
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DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
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DIEPMSK_INTKNEPMISMSK,
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DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
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hsotg->regs + DIEPMSK);
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/*
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* don't need XferCompl, we get that from RXFIFO in slave mode. In
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* DMA mode we may need this.
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*/
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dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
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DIEPMSK_TIMEOUTMSK) : 0) |
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dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK) : 0) |
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DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
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DOEPMSK_SETUPMSK,
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DOEPMSK_SETUPMSK | DOEPMSK_STSPHSERCVDMSK,
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hsotg->regs + DOEPMSK);
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dwc2_writel(0, hsotg->regs + DAINTMSK);
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@ -2858,11 +2882,29 @@ irq_retry:
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*/
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if (gintsts & GINTSTS_GOUTNAKEFF) {
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dev_info(hsotg->dev, "GOUTNakEff triggered\n");
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u8 idx;
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u32 epctrl;
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u32 gintmsk;
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struct dwc2_hsotg_ep *hs_ep;
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__orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
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/* Mask this interrupt */
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gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
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gintmsk &= ~GINTSTS_GOUTNAKEFF;
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dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
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dwc2_hsotg_dump(hsotg);
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dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
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for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
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hs_ep = hsotg->eps_out[idx];
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epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
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if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
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epctrl |= DXEPCTL_SNAK;
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epctrl |= DXEPCTL_EPDIS;
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dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
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}
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}
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/* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
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}
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if (gintsts & GINTSTS_GINNAKEFF) {
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@ -2909,6 +2951,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
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u32 epctrl_reg;
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u32 epctrl;
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u32 mps;
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u32 mask;
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unsigned int dir_in;
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unsigned int i, val, size;
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int ret = 0;
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@ -2951,15 +2994,6 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
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*/
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epctrl |= DXEPCTL_USBACTEP;
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/*
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* set the NAK status on the endpoint, otherwise we might try and
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* do something with data that we've yet got a request to process
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* since the RXFIFO will take data for an endpoint even if the
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* size register hasn't been set.
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*/
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epctrl |= DXEPCTL_SNAK;
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/* update the endpoint state */
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dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
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@ -2975,8 +3009,17 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
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epctrl |= DXEPCTL_SETEVENFR;
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hs_ep->isochronous = 1;
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hs_ep->interval = 1 << (desc->bInterval - 1);
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if (dir_in)
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hs_ep->target_frame = TARGET_FRAME_INITIAL;
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if (dir_in) {
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hs_ep->periodic = 1;
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mask = dwc2_readl(hsotg->regs + DIEPMSK);
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mask |= DIEPMSK_NAKMSK;
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dwc2_writel(mask, hsotg->regs + DIEPMSK);
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} else {
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mask = dwc2_readl(hsotg->regs + DOEPMSK);
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mask |= DOEPMSK_OUTTKNEPDISMSK;
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dwc2_writel(mask, hsotg->regs + DOEPMSK);
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}
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break;
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case USB_ENDPOINT_XFER_BULK:
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@ -3043,7 +3086,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
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}
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/* for non control endpoints, set PID to D0 */
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if (index)
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if (index && !hs_ep->isochronous)
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epctrl |= DXEPCTL_SETD0PID;
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dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
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@ -560,6 +560,7 @@
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#define DXEPINT_INEPNAKEFF (1 << 6)
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#define DXEPINT_BACK2BACKSETUP (1 << 6)
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#define DXEPINT_INTKNEPMIS (1 << 5)
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#define DXEPINT_STSPHSERCVD (1 << 5)
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#define DXEPINT_INTKNTXFEMP (1 << 4)
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#define DXEPINT_OUTTKNEPDIS (1 << 4)
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#define DXEPINT_TIMEOUT (1 << 3)
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