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Blackfin: split optimization settings more
We need to place icache flush funcs into L1 inst sram to work around a hardware anomaly. But this currently breaks SMP support as the L1 inst sram is per-core and cannot be called directly. So in preparation for making that work, split the two options. Further, split out the SMP depend so that we can allow some for SMP. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger
parent
567ebfc99d
commit
820b127dae
@ -690,13 +690,13 @@ endmenu
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menu "Blackfin Kernel Optimizations"
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depends on !SMP
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comment "Memory Optimizations"
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config I_ENTRY_L1
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bool "Locate interrupt entry code in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
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into L1 instruction memory. (less latency)
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@ -704,6 +704,7 @@ config I_ENTRY_L1
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config EXCPT_IRQ_SYSC_L1
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bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the entire ASM lowlevel exception and interrupt entry code
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(STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
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@ -712,6 +713,7 @@ config EXCPT_IRQ_SYSC_L1
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config DO_IRQ_L1
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bool "Locate frequently called do_irq dispatcher function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the frequently called do_irq dispatcher function is linked
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into L1 instruction memory. (less latency)
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@ -719,6 +721,7 @@ config DO_IRQ_L1
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config CORE_TIMER_IRQ_L1
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bool "Locate frequently called timer_interrupt() function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the frequently called timer_interrupt() function is linked
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into L1 instruction memory. (less latency)
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@ -726,6 +729,7 @@ config CORE_TIMER_IRQ_L1
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config IDLE_L1
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bool "Locate frequently idle function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the frequently called idle function is linked
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into L1 instruction memory. (less latency)
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@ -733,6 +737,7 @@ config IDLE_L1
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config SCHEDULE_L1
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bool "Locate kernel schedule function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the frequently called kernel schedule is linked
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into L1 instruction memory. (less latency)
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@ -740,6 +745,7 @@ config SCHEDULE_L1
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config ARITHMETIC_OPS_L1
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bool "Locate kernel owned arithmetic functions in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, arithmetic functions are linked
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into L1 instruction memory. (less latency)
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@ -747,6 +753,7 @@ config ARITHMETIC_OPS_L1
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config ACCESS_OK_L1
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bool "Locate access_ok function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the access_ok function is linked
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into L1 instruction memory. (less latency)
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@ -754,6 +761,7 @@ config ACCESS_OK_L1
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config MEMSET_L1
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bool "Locate memset function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the memset function is linked
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into L1 instruction memory. (less latency)
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@ -761,6 +769,7 @@ config MEMSET_L1
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config MEMCPY_L1
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bool "Locate memcpy function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the memcpy function is linked
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into L1 instruction memory. (less latency)
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@ -768,6 +777,7 @@ config MEMCPY_L1
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config STRCMP_L1
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bool "locate strcmp function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the strcmp function is linked
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into L1 instruction memory (less latency).
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@ -775,6 +785,7 @@ config STRCMP_L1
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config STRNCMP_L1
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bool "locate strncmp function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the strncmp function is linked
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into L1 instruction memory (less latency).
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@ -782,6 +793,7 @@ config STRNCMP_L1
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config STRCPY_L1
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bool "locate strcpy function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the strcpy function is linked
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into L1 instruction memory (less latency).
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@ -789,6 +801,7 @@ config STRCPY_L1
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config STRNCPY_L1
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bool "locate strncpy function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, the strncpy function is linked
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into L1 instruction memory (less latency).
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@ -796,6 +809,7 @@ config STRNCPY_L1
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config SYS_BFIN_SPINLOCK_L1
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bool "Locate sys_bfin_spinlock function in L1 Memory"
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default y
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depends on !SMP
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help
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If enabled, sys_bfin_spinlock function is linked
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into L1 instruction memory. (less latency)
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@ -803,6 +817,7 @@ config SYS_BFIN_SPINLOCK_L1
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config IP_CHECKSUM_L1
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bool "Locate IP Checksum function in L1 Memory"
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default n
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depends on !SMP
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help
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If enabled, the IP Checksum function is linked
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into L1 instruction memory. (less latency)
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@ -811,7 +826,7 @@ config CACHELINE_ALIGNED_L1
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bool "Locate cacheline_aligned data to L1 Data Memory"
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default y if !BF54x
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default n if BF54x
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depends on !BF531
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depends on !SMP && !BF531
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help
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If enabled, cacheline_aligned data is linked
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into L1 data memory. (less latency)
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@ -819,7 +834,7 @@ config CACHELINE_ALIGNED_L1
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config SYSCALL_TAB_L1
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bool "Locate Syscall Table L1 Data Memory"
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default n
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depends on !BF531
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depends on !SMP && !BF531
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help
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If enabled, the Syscall LUT is linked
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into L1 data memory. (less latency)
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@ -827,16 +842,17 @@ config SYSCALL_TAB_L1
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config CPLB_SWITCH_TAB_L1
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bool "Locate CPLB Switch Tables L1 Data Memory"
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default n
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depends on !BF531
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depends on !SMP && !BF531
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help
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If enabled, the CPLB Switch Tables are linked
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into L1 data memory. (less latency)
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config CACHE_FLUSH_L1
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bool "Locate cache flush funcs in L1 Inst Memory"
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config ICACHE_FLUSH_L1
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bool "Locate icache flush funcs in L1 Inst Memory"
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default y
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depends on !SMP
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help
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If enabled, the Blackfin cache flushing functions are linked
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If enabled, the Blackfin icache flushing functions are linked
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into L1 instruction memory.
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Note that this might be required to address anomalies, but
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@ -844,9 +860,18 @@ config CACHE_FLUSH_L1
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If you are using a processor affected by an anomaly, the build
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system will double check for you and prevent it.
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config DCACHE_FLUSH_L1
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bool "Locate dcache flush funcs in L1 Inst Memory"
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default y
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depends on !SMP
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help
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If enabled, the Blackfin dcache flushing functions are linked
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into L1 instruction memory.
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config APP_STACK_L1
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bool "Support locating application stack in L1 Scratch Memory"
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default y
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depends on !SMP
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help
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If enabled the application stack can be located in L1
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scratch memory (less latency).
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@ -856,7 +881,7 @@ config APP_STACK_L1
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config EXCEPTION_L1_SCRATCH
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bool "Locate exception stack in L1 Scratch Memory"
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default n
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depends on !APP_STACK_L1
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depends on !SMP && !APP_STACK_L1
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help
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Whenever an exception occurs, use the L1 Scratch memory for
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stack storage. You cannot place the stacks of FLAT binaries
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@ -868,6 +893,7 @@ comment "Speed Optimizations"
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config BFIN_INS_LOWOVERHEAD
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bool "ins[bwl] low overhead, higher interrupt latency"
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default y
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depends on !SMP
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help
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Reads on the Blackfin are speculative. In Blackfin terms, this means
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they can be interrupted at any time (even after they have been issued
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@ -61,6 +61,6 @@
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# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
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#endif
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#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1)
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#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
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# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
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#endif
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@ -11,12 +11,6 @@
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#include <asm/cache.h>
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#include <asm/page.h>
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#ifdef CONFIG_CACHE_FLUSH_L1
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.section .l1.text
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#else
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.text
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#endif
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/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
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#if ANOMALY_05000443
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# define BROK_FLUSH_INST "IFLUSH"
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@ -68,11 +62,23 @@
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RTS;
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.endm
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#ifdef CONFIG_ICACHE_FLUSH_L1
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.section .l1.text
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#else
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.text
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#endif
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/* Invalidate all instruction cache lines assocoiated with this memory area */
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ENTRY(_blackfin_icache_flush_range)
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do_flush IFLUSH
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ENDPROC(_blackfin_icache_flush_range)
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#ifdef CONFIG_DCACHE_FLUSH_L1
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.section .l1.text
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#else
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.text
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#endif
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/* Throw away all D-cached data in specified region without any obligation to
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* write them back. Since the Blackfin ISA does not have an "invalidate"
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* instruction, we use flush/invalidate. Perhaps as a speed optimization we
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