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thermal: tegra: add Tegra210 specific SOC_THERM driver
Add Tegra210 specific SOC_THERM driver. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
This commit is contained in:
Wei Ni
Eduardo Valentin
parent
65b6d57c24
commit
8204104f35
@ -2,3 +2,4 @@ obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
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tegra-soctherm-y := soctherm.o soctherm-fuse.o
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tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o
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tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-soctherm.o
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@ -28,7 +28,18 @@
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#define FUSE_TSENSOR_COMMON 0x180
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/*
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* Tegra210: Layout of bits in FUSE_TSENSOR_COMMON:
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* 3 2 1 0
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* Tegra12x, etc:
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* In chips prior to Tegra210, this fuse was incorrectly sized as 26 bits,
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* and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits
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* were obtained via the FUSE_SPARE_REALIGNMENT_REG register [5:0].
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*
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* FUSE_TSENSOR_COMMON:
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* 3 2 1 0
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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@ -146,6 +146,12 @@ static const struct of_device_id tegra_soctherm_of_match[] = {
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.compatible = "nvidia,tegra124-soctherm",
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.data = &tegra124_soctherm,
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},
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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{
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.compatible = "nvidia,tegra210-soctherm",
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.data = &tegra210_soctherm,
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},
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#endif
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{ },
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};
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@ -106,5 +106,9 @@ int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
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extern const struct tegra_soctherm_soc tegra124_soctherm;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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extern const struct tegra_soctherm_soc tegra210_soctherm;
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#endif
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#endif
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173
drivers/thermal/tegra/tegra210-soctherm.c
Normal file
173
drivers/thermal/tegra/tegra210-soctherm.c
Normal file
@ -0,0 +1,173 @@
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/*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/fuse.h>
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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#include "soctherm.h"
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static const struct tegra_tsensor_configuration tegra210_tsensor_config = {
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.tall = 16300,
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.tiddq_en = 1,
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.ten_count = 1,
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.tsample = 120,
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.tsample_ate = 480,
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};
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static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_CPU,
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.name = "cpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_CPU_MASK,
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.pllx_hotspot_diff = 10,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
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};
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static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = {
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.id = TEGRA124_SOCTHERM_SENSOR_GPU,
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.name = "gpu",
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.sensor_temp_offset = SENSOR_TEMP1,
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.sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_GPU_MASK,
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.pllx_hotspot_diff = 5,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
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};
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static const struct tegra_tsensor_group tegra210_tsensor_group_pll = {
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.id = TEGRA124_SOCTHERM_SENSOR_PLLX,
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.name = "pll",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_PLLX_MASK,
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};
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static const struct tegra_tsensor_group tegra210_tsensor_group_mem = {
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.id = TEGRA124_SOCTHERM_SENSOR_MEM,
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.name = "mem",
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.sensor_temp_offset = SENSOR_TEMP2,
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.sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
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.pdiv = 8,
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.pdiv_ate = 8,
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.pdiv_mask = SENSOR_PDIV_MEM_MASK,
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.pllx_hotspot_diff = 0,
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.pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
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};
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static const struct tegra_tsensor_group *tegra210_tsensor_groups[] = {
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&tegra210_tsensor_group_cpu,
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&tegra210_tsensor_group_gpu,
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&tegra210_tsensor_group_pll,
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&tegra210_tsensor_group_mem,
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};
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static const struct tegra_tsensor tegra210_tsensors[] = {
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{
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.name = "cpu0",
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.base = 0xc0,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x098,
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.fuse_corr_alpha = 1085000,
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.fuse_corr_beta = 3244200,
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.group = &tegra210_tsensor_group_cpu,
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}, {
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.name = "cpu1",
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.base = 0xe0,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x084,
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.fuse_corr_alpha = 1126200,
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.fuse_corr_beta = -67500,
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.group = &tegra210_tsensor_group_cpu,
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}, {
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.name = "cpu2",
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.base = 0x100,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x088,
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.fuse_corr_alpha = 1098400,
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.fuse_corr_beta = 2251100,
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.group = &tegra210_tsensor_group_cpu,
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}, {
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.name = "cpu3",
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.base = 0x120,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x12c,
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.fuse_corr_alpha = 1108000,
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.fuse_corr_beta = 602700,
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.group = &tegra210_tsensor_group_cpu,
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}, {
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.name = "mem0",
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.base = 0x140,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x158,
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.fuse_corr_alpha = 1069200,
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.fuse_corr_beta = 3549900,
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.group = &tegra210_tsensor_group_mem,
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}, {
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.name = "mem1",
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.base = 0x160,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x15c,
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.fuse_corr_alpha = 1173700,
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.fuse_corr_beta = -6263600,
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.group = &tegra210_tsensor_group_mem,
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}, {
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.name = "gpu",
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.base = 0x180,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x154,
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.fuse_corr_alpha = 1074300,
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.fuse_corr_beta = 2734900,
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.group = &tegra210_tsensor_group_gpu,
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}, {
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.name = "pllx",
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.base = 0x1a0,
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.config = &tegra210_tsensor_config,
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.calib_fuse_offset = 0x160,
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.fuse_corr_alpha = 1039700,
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.fuse_corr_beta = 6829100,
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.group = &tegra210_tsensor_group_pll,
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},
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};
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/*
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* Mask/shift bits in FUSE_TSENSOR_COMMON and
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* FUSE_TSENSOR_COMMON, which are described in
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* tegra_soctherm_fuse.c
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*/
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static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
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.fuse_base_cp_mask = 0x3ff << 11,
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.fuse_base_cp_shift = 11,
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.fuse_base_ft_mask = 0x7ff << 21,
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.fuse_base_ft_shift = 21,
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.fuse_shift_ft_mask = 0x1f << 6,
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.fuse_shift_ft_shift = 6,
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.fuse_spare_realignment = 0,
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};
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const struct tegra_soctherm_soc tegra210_soctherm = {
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.tsensors = tegra210_tsensors,
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.num_tsensors = ARRAY_SIZE(tegra210_tsensors),
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.ttgs = tegra210_tsensor_groups,
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.num_ttgs = ARRAY_SIZE(tegra210_tsensor_groups),
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.tfuse = &tegra210_soctherm_fuse,
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};
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