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drm/nvd0/disp: use single, shared, sync bo for all evo channels
This simplifies some things, and hopefully won't come back to bite me. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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a63a97eb66
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@ -43,12 +43,17 @@
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#define EVO_OIMM(c) (0x09 + (c))
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#define EVO_CURS(c) (0x0d + (c))
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/* offsets in shared sync bo of various structures */
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#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
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#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
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#define EVO_FLIP_SEM0(c) EVO_SYNC((c), 0x00)
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#define EVO_FLIP_SEM1(c) EVO_SYNC((c), 0x10)
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struct evo {
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int idx;
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dma_addr_t handle;
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u32 *ptr;
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struct {
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struct nouveau_bo *bo;
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u32 offset;
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u16 value;
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} sem;
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@ -56,6 +61,7 @@ struct evo {
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struct nvd0_display {
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struct nouveau_gpuobj *mem;
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struct nouveau_bo *sync;
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struct evo evo[9];
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struct tasklet_struct tasklet;
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@ -212,27 +218,23 @@ evo_fini_pio(struct drm_device *dev, int ch)
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static bool
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evo_sync_wait(void *data)
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{
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return nouveau_bo_rd32(data, 0) != 0x00000000;
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return nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000;
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}
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static int
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evo_sync(struct drm_device *dev, int ch)
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{
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struct nvd0_display *disp = nvd0_display(dev);
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struct evo *evo = &disp->evo[ch];
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u32 *push;
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nouveau_bo_wr32(evo->sem.bo, 0, 0x00000000);
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push = evo_wait(dev, ch, 8);
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u32 *push = evo_wait(dev, ch, 8);
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if (push) {
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nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
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evo_mthd(push, 0x0084, 1);
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evo_data(push, 0x80000000);
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evo_data(push, 0x80000000 | EVO_MAST_NTFY);
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evo_mthd(push, 0x0080, 2);
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evo_data(push, 0x00000000);
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evo_data(push, 0x00000000);
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evo_kick(push, dev, ch);
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if (nv_wait_cb(dev, evo_sync_wait, evo->sem.bo))
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if (nv_wait_cb(dev, evo_sync_wait, disp->sync))
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return 0;
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}
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@ -245,9 +247,7 @@ evo_sync(struct drm_device *dev, int ch)
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struct nouveau_bo *
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nvd0_display_crtc_sema(struct drm_device *dev, int crtc)
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{
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struct nvd0_display *disp = nvd0_display(dev);
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struct evo *evo = &disp->evo[EVO_FLIP(crtc)];
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return evo->sem.bo;
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return nvd0_display(dev)->sync;
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}
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void
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@ -313,7 +313,7 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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OUT_RING (chan, 0x1001);
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FIRE_RING (chan);
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} else {
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nouveau_bo_wr32(evo->sem.bo, evo->sem.offset / 4,
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nouveau_bo_wr32(disp->sync, evo->sem.offset / 4,
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0xf00d0000 | evo->sem.value);
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evo_sync(crtc->dev, EVO_MASTER);
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}
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@ -1752,12 +1752,12 @@ nvd0_display_destroy(struct drm_device *dev)
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for (i = 0; i < EVO_DMA_NR; i++) {
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struct evo *evo = &disp->evo[i];
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nouveau_bo_unmap(evo->sem.bo);
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nouveau_bo_ref(NULL, &evo->sem.bo);
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pci_free_consistent(pdev, PAGE_SIZE, evo->ptr, evo->handle);
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}
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nouveau_gpuobj_ref(NULL, &disp->mem);
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nouveau_bo_unmap(disp->sync);
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nouveau_bo_ref(NULL, &disp->sync);
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nouveau_irq_unregister(dev, 26);
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dev_priv->engine.display.priv = NULL;
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@ -1829,6 +1829,20 @@ nvd0_display_create(struct drm_device *dev)
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tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev);
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nouveau_irq_register(dev, 26, nvd0_display_intr);
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/* small shared memory area we use for notifiers and semaphores */
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ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
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0, 0x0000, &disp->sync);
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if (!ret) {
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ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
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if (!ret)
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ret = nouveau_bo_map(disp->sync);
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if (ret)
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nouveau_bo_ref(NULL, &disp->sync);
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}
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if (ret)
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goto out;
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/* hash table and dma objects for the memory areas we care about */
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ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
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NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
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@ -1838,31 +1852,18 @@ nvd0_display_create(struct drm_device *dev)
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/* create evo dma channels */
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for (i = 0; i < EVO_DMA_NR; i++) {
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struct evo *evo = &disp->evo[i];
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u64 offset = disp->sync->bo.offset;
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u32 dmao = 0x1000 + (i * 0x100);
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u32 hash = 0x0000 + (i * 0x040);
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u64 offset;
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evo->idx = i;
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evo->sem.offset = EVO_SYNC(evo->idx, 0x00);
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evo->ptr = pci_alloc_consistent(pdev, PAGE_SIZE, &evo->handle);
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if (!evo->ptr) {
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ret = -ENOMEM;
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goto out;
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}
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ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
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0, 0x0000, &evo->sem.bo);
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if (!ret) {
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ret = nouveau_bo_pin(evo->sem.bo, TTM_PL_FLAG_VRAM);
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if (!ret)
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ret = nouveau_bo_map(evo->sem.bo);
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if (ret)
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nouveau_bo_ref(NULL, &evo->sem.bo);
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offset = evo->sem.bo->bo.offset;
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}
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if (ret)
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goto out;
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nv_wo32(disp->mem, dmao + 0x00, 0x00000049);
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nv_wo32(disp->mem, dmao + 0x04, (offset + 0x0000) >> 8);
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nv_wo32(disp->mem, dmao + 0x08, (offset + 0x0fff) >> 8);
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