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https://github.com/edk2-porting/linux-next.git
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ARM: dts: Add devicetree for Eckelmann ci4x10
This is one of two boards that make use of the recently introduced SIOX bus. Apart from the devices described in the dts it features a display with touch that I didn't include here because it needs some non-mainline change to operate correctly. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Uwe Kleine-König
Shawn Guo
parent
26d459398a
commit
811c94f1e8
@ -400,6 +400,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
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imx6dl-cubox-i-emmc-som-v15.dtb \
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imx6dl-cubox-i-som-v15.dtb \
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imx6dl-dfi-fs700-m60.dtb \
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imx6dl-eckelmann-ci4x10.dtb \
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imx6dl-emcon-avari.dtb \
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imx6dl-gw51xx.dtb \
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imx6dl-gw52xx.dtb \
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381
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
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381
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
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@ -0,0 +1,381 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 Eckelmann AG.
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "imx6dl.dtsi"
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/ {
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model = "Eckelmann CI 4X10 Board";
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compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
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chosen {
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stdout-path = &uart3;
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};
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x40000000>;
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};
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rmii_clk: clock-rmii {
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/* This clock is provided by the phy (KSZ8091RNB) */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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reg_usb_h1_vbus: regulator-usb-h1-vbus {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
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compatible = "regulator-fixed";
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regulator-name = "usb_h1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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siox {
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compatible = "eckelmann,siox-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_siox>;
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din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
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dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
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dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
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dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
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status = "okay";
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flash@0 {
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compatible = "everspin,mr25h256";
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reg = <0>;
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spi-max-frequency = <15000000>;
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};
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
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status = "okay";
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tpm@0 {
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compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
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reg = <0>;
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spi-max-frequency = <10000000>;
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};
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};
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&gpio2 {
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gpio-line-names = "buzzer", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio4 {
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gpio-line-names = "", "", "", "", "", "", "", "in2",
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"prio2", "prio1", "aux", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&gpio6 {
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gpio-line-names = "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "in1",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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temperature-sensor@49 {
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compatible = "ad,ad7414";
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reg = <0x49>;
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};
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rtc@51 {
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compatible = "nxp,pcf2127";
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reg = <0x51>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hog {
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fsl,pins = <
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MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */
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MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */
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MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */
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MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
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MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
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MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */
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MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0
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MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0
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MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0
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MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1
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MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1
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MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1
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MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
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MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0
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MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020
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MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020
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MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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/* without SION i2c doesn't detect bus busy */
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MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820
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MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820
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>;
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};
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018
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>;
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};
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pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0
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>;
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};
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pinctrl_siox: sioxgrp {
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fsl,pins = <
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MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */
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MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */
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MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
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MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */
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>;
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};
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pinctrl_uart1_dte: uart1grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010
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MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010
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MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010
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MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010
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MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */
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MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
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MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */
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>;
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};
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pinctrl_uart2_dte: uart2grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010
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MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010
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MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010
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MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010
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MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */
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MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
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MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */
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>;
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};
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pinctrl_uart3_dce: uart3grp {
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fsl,pins = <
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MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010
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MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010
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>;
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};
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pinctrl_uart4_dce: uart4grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010
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MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010
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MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010
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>;
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};
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pinctrl_uart5_dce: uart5grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010
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MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010
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MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */
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>;
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};
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pinctrl_usbh1: usbh1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059
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MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059
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MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059
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MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059
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MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059
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>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
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phy-handle = <&phy>;
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clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_dte>;
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uart-has-rtscts;
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fsl,dte-mode;
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dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2_dte>;
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uart-has-rtscts;
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fsl,dte-mode;
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dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3_dce>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart4_dce>;
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rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5_dce>;
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rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&usbh1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbh1>;
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vbus-supply = <®_usb_h1_vbus>;
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status = "okay";
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};
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&usbotg {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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