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drm/i915: Store a pointer to the pixel format info for fbc

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Rather than store the pixel format and look up the format info as
needed,  let's just store a pointer to the format info directly
and speed up our lookups.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1479498793-31021-29-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2016-11-18 21:53:04 +02:00
parent 9857ecbe51
commit 801c8fe831
2 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/i915_drv.h
View File

@ -1026,7 +1026,7 @@ struct intel_fbc {
struct {
u64 ilk_ggtt_offset;
uint32_t pixel_format;
const struct drm_format_info *format;
unsigned int stride;
int fence_reg;
unsigned int tiling_mode;
@ -1042,7 +1042,7 @@ struct intel_fbc {
struct {
u64 ggtt_offset;
uint32_t pixel_format;
const struct drm_format_info *format;
unsigned int stride;
int fence_reg;
} fb;

14
drivers/gpu/drm/i915/intel_fbc.c
View File

@ -188,7 +188,7 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
u32 dpfc_ctl;
dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
if (params->fb.format->cpp[0] == 2)
dpfc_ctl |= DPFC_CTL_LIMIT_2X;
else
dpfc_ctl |= DPFC_CTL_LIMIT_1X;
@ -235,7 +235,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
int threshold = dev_priv->fbc.threshold;
dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
if (params->fb.format->cpp[0] == 2)
threshold++;
switch (threshold) {
@ -303,7 +303,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
if (IS_IVYBRIDGE(dev_priv))
dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
if (drm_format_plane_cpp(params->fb.pixel_format, 0) == 2)
if (params->fb.format->cpp[0] == 2)
threshold++;
switch (threshold) {
@ -581,7 +581,7 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
fb_cpp = drm_format_plane_cpp(fbc->state_cache.fb.pixel_format, 0);
fb_cpp = fbc->state_cache.fb.format->cpp[0];
ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
size, fb_cpp);
@ -764,7 +764,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
* platforms that need. */
if (IS_GEN(dev_priv, 5, 6))
cache->fb.ilk_ggtt_offset = i915_gem_object_ggtt_offset(obj, NULL);
cache->fb.pixel_format = fb->pixel_format;
cache->fb.format = fb->format;
cache->fb.stride = fb->pitches[0];
cache->fb.fence_reg = get_fence_id(fb);
cache->fb.tiling_mode = i915_gem_object_get_tiling(obj);
@ -823,7 +823,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
return false;
}
if (!pixel_format_is_valid(dev_priv, cache->fb.pixel_format)) {
if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
fbc->no_fbc_reason = "pixel format is invalid";
return false;
}
@ -892,7 +892,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
params->crtc.plane = crtc->plane;
params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
params->fb.pixel_format = cache->fb.pixel_format;
params->fb.format = cache->fb.format;
params->fb.stride = cache->fb.stride;
params->fb.fence_reg = cache->fb.fence_reg;