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synced 2024-12-25 21:54:06 +08:00
drm/radeon: remove range check from *_gart_set_page
We never check the return value anyway and if the index isn't valid would crash way before calling the functions. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0986c1a55c
commit
7f90fc9650
@ -682,15 +682,11 @@ void r100_pci_gart_disable(struct radeon_device *rdev)
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WREG32(RADEON_AIC_HI_ADDR, 0);
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}
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int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
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uint64_t addr)
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{
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u32 *gtt = rdev->gart.ptr;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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gtt[i] = cpu_to_le32(lower_32_bits(addr));
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return 0;
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}
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void r100_pci_gart_fini(struct radeon_device *rdev)
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@ -72,13 +72,11 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
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#define R300_PTE_WRITEABLE (1 << 2)
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#define R300_PTE_READABLE (1 << 3)
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int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
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uint64_t addr)
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{
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void __iomem *ptr = rdev->gart.ptr;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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addr = (lower_32_bits(addr) >> 8) |
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((upper_32_bits(addr) & 0xff) << 24) |
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R300_PTE_WRITEABLE | R300_PTE_READABLE;
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@ -86,7 +84,6 @@ int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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* on powerpc without HW swappers, it'll get swapped on way
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* into VRAM - so no need for cpu_to_le32 on VRAM tables */
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writel(addr, ((void __iomem *)ptr) + (i * 4));
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return 0;
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}
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int rv370_pcie_gart_init(struct radeon_device *rdev)
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@ -1782,7 +1782,8 @@ struct radeon_asic {
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/* gart */
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struct {
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void (*tlb_flush)(struct radeon_device *rdev);
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int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
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void (*set_page)(struct radeon_device *rdev, unsigned i,
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uint64_t addr);
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} gart;
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struct {
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int (*init)(struct radeon_device *rdev);
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@ -67,7 +67,8 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
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int r100_asic_reset(struct radeon_device *rdev);
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u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
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void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
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int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
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void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
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uint64_t addr);
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void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
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int r100_irq_set(struct radeon_device *rdev);
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int r100_irq_process(struct radeon_device *rdev);
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@ -171,7 +172,8 @@ extern void r300_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence);
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extern int r300_cs_parse(struct radeon_cs_parser *p);
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extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
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extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
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extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
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uint64_t addr);
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extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
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extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
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extern void r300_set_reg_safe(struct radeon_device *rdev);
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@ -206,7 +208,8 @@ extern void rs400_fini(struct radeon_device *rdev);
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extern int rs400_suspend(struct radeon_device *rdev);
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extern int rs400_resume(struct radeon_device *rdev);
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void rs400_gart_tlb_flush(struct radeon_device *rdev);
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int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
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void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
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uint64_t addr);
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uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
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void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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int rs400_gart_init(struct radeon_device *rdev);
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@ -229,7 +232,8 @@ int rs600_irq_process(struct radeon_device *rdev);
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void rs600_irq_disable(struct radeon_device *rdev);
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u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
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void rs600_gart_tlb_flush(struct radeon_device *rdev);
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int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
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void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
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uint64_t addr);
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uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
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void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
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void rs600_bandwidth_update(struct radeon_device *rdev);
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@ -212,21 +212,16 @@ void rs400_gart_fini(struct radeon_device *rdev)
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#define RS400_PTE_WRITEABLE (1 << 2)
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#define RS400_PTE_READABLE (1 << 3)
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int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, uint64_t addr)
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{
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uint32_t entry;
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u32 *gtt = rdev->gart.ptr;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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entry = (lower_32_bits(addr) & PAGE_MASK) |
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((upper_32_bits(addr) & 0xff) << 4) |
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RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
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entry = cpu_to_le32(entry);
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gtt[i] = entry;
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return 0;
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}
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int rs400_mc_wait_for_idle(struct radeon_device *rdev)
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@ -626,20 +626,16 @@ static void rs600_gart_fini(struct radeon_device *rdev)
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radeon_gart_table_vram_free(rdev);
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}
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int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, uint64_t addr)
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{
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void __iomem *ptr = (void *)rdev->gart.ptr;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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addr = addr & 0xFFFFFFFFFFFFF000ULL;
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if (addr == rdev->dummy_page.addr)
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addr |= R600_PTE_SYSTEM | R600_PTE_SNOOPED;
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else
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addr |= R600_PTE_GART;
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writeq(addr, ptr + (i * 8));
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return 0;
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}
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int rs600_irq_set(struct radeon_device *rdev)
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