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clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI
There is no case (and none foreseen) where we would need to disable the SDn clock. So, for simplicity, remove its handling. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20200922120036.10298-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -224,10 +224,9 @@ static struct clk * __init cpg_z_clk_register(const char *name,
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#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
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#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
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#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
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#define CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) \
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{ \
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.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
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((stp_ck) ? CPG_SD_STP_CK : 0) | \
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((sd_srcfc) << 2) | \
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((sd_fc) << 0), \
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.div = (sd_div), \
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@ -247,36 +246,36 @@ struct sd_clock {
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};
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/* SDn divider
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* sd_srcfc sd_fc div
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* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
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*-------------------------------------------------------------------
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* 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
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* 0 0 1 (2) 1 (4) 8 : SDR50
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* 1 0 2 (4) 1 (4) 16 : HS / SDR25
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* 1 0 3 (8) 1 (4) 32 : NS / SDR12
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* 1 0 4 (16) 1 (4) 64
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* 0 0 0 (1) 0 (2) 2
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* 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
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* 1 0 2 (4) 0 (2) 8
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* 1 0 3 (8) 0 (2) 16
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* 1 0 4 (16) 0 (2) 32
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* sd_srcfc sd_fc div
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* stp_hck (div) (div) = sd_srcfc x sd_fc
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*---------------------------------------------------------
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* 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
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* 0 1 (2) 1 (4) 8 : SDR50
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* 1 2 (4) 1 (4) 16 : HS / SDR25
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* 1 3 (8) 1 (4) 32 : NS / SDR12
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* 1 4 (16) 1 (4) 64
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* 0 0 (1) 0 (2) 2
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* 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
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* 1 2 (4) 0 (2) 8
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* 1 3 (8) 0 (2) 16
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* 1 4 (16) 0 (2) 32
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*
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* NOTE: There is a quirk option to ignore the first row of the dividers
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* table when searching for suitable settings. This is because HS400 on
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* early ES versions of H3 and M3-W requires a specific setting to work.
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*/
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static const struct sd_div_table cpg_sd_div_table[] = {
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/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
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/* CPG_SD_DIV_TABLE_DATA(stp_hck, sd_srcfc, sd_fc, sd_div) */
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 4),
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CPG_SD_DIV_TABLE_DATA(0, 1, 1, 8),
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CPG_SD_DIV_TABLE_DATA(1, 2, 1, 16),
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CPG_SD_DIV_TABLE_DATA(1, 3, 1, 32),
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CPG_SD_DIV_TABLE_DATA(1, 4, 1, 64),
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 2),
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CPG_SD_DIV_TABLE_DATA(0, 1, 0, 4),
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CPG_SD_DIV_TABLE_DATA(1, 2, 0, 8),
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CPG_SD_DIV_TABLE_DATA(1, 3, 0, 16),
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CPG_SD_DIV_TABLE_DATA(1, 4, 0, 32),
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};
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#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
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