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drm/amd/display: Add DCN2 HW Sequencer and Resource

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Add DCN2 resource definition and HW Sequencer changes.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2019-02-22 16:52:08 -05:00 committed by Alex Deucher
parent 18eaea4bf8
commit 7ed4e6352c
13 changed files with 5246 additions and 1 deletions
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15
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View File

@ -46,6 +46,9 @@
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn10/dcn10_resource.h"
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#include "dcn20/dcn20_resource.h"
#endif
#include "dce120/dce120_resource.h"
#define DC_LOGGER_INIT(logger)
@ -97,6 +100,12 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
dc_version = DCN_VERSION_1_01;
break;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
case FAMILY_NV:
dc_version = DCN_VERSION_2_0;
break;
#endif
default:
dc_version = DCE_VERSION_UNKNOWN;
break;
@ -151,6 +160,12 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
case DCN_VERSION_2_0:
res_pool = dcn20_create_resource_pool(init_data, dc);
break;
#endif
default:
break;
}

88
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
View File

@ -726,6 +726,56 @@ static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)
#endif //(CONFIG_DRM_AMD_DC_DCN1_0)
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
static bool dcn20_lock_phy(struct dmcu *dmcu)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
/* If microcontroller is not running, do nothing */
if (dmcu->dmcu_state != DMCU_RUNNING)
return false;
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
/* setDMCUParam_Cmd */
REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_LOCK);
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
return true;
}
static bool dcn20_unlock_phy(struct dmcu *dmcu)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
/* If microcontroller is not running, do nothing */
if (dmcu->dmcu_state != DMCU_RUNNING)
return false;
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
/* setDMCUParam_Cmd */
REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_SYNC_PHY_UNLOCK);
/* notifyDMCUMsg */
REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
/* waitDMCUReadyForCmd */
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);
return true;
}
#endif //(CONFIG_DRM_AMD_DC_DCN2_0)
static const struct dmcu_funcs dce_funcs = {
.dmcu_init = dce_dmcu_init,
.load_iram = dce_dmcu_load_iram,
@ -750,6 +800,21 @@ static const struct dmcu_funcs dcn10_funcs = {
};
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
static const struct dmcu_funcs dcn20_funcs = {
.dmcu_init = dcn10_dmcu_init,
.load_iram = dcn10_dmcu_load_iram,
.set_psr_enable = dcn10_dmcu_set_psr_enable,
.setup_psr = dcn10_dmcu_setup_psr,
.get_psr_state = dcn10_get_dmcu_psr_state,
.set_psr_wait_loop = dcn10_psr_wait_loop,
.get_psr_wait_loop = dcn10_get_psr_wait_loop,
.is_dmcu_initialized = dcn10_is_dmcu_initialized,
.lock_phy = dcn20_lock_phy,
.unlock_phy = dcn20_unlock_phy
};
#endif
static void dce_dmcu_construct(
struct dce_dmcu *dmcu_dce,
struct dc_context *ctx,
@ -812,6 +877,29 @@ struct dmcu *dcn10_dmcu_create(
}
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct dmcu *dcn20_dmcu_create(
struct dc_context *ctx,
const struct dce_dmcu_registers *regs,
const struct dce_dmcu_shift *dmcu_shift,
const struct dce_dmcu_mask *dmcu_mask)
{
struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL);
if (dmcu_dce == NULL) {
BREAK_TO_DEBUGGER();
return NULL;
}
dce_dmcu_construct(
dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask);
dmcu_dce->base.funcs = &dcn20_funcs;
return &dmcu_dce->base;
}
#endif
void dce_dmcu_destroy(struct dmcu **dmcu)
{
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);

8
drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h
View File

@ -261,6 +261,14 @@ struct dmcu *dcn10_dmcu_create(
const struct dce_dmcu_shift *dmcu_shift,
const struct dce_dmcu_mask *dmcu_mask);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct dmcu *dcn20_dmcu_create(
struct dc_context *ctx,
const struct dce_dmcu_registers *regs,
const struct dce_dmcu_shift *dmcu_shift,
const struct dce_dmcu_mask *dmcu_mask);
#endif
void dce_dmcu_destroy(struct dmcu **dmcu);
static const uint32_t abm_gain_stepsize = 0x0060;

127
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
View File

@ -199,6 +199,70 @@
SR(DC_IP_REQUEST_CNTL), \
BL_REG_LIST()
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#define HWSEQ_DCN2_REG_LIST()\
HWSEQ_DCN_REG_LIST(), \
HWSEQ_PIXEL_RATE_REG_LIST(OTG), \
HWSEQ_PHYPLL_REG_LIST(OTG), \
SR(MICROSECOND_TIME_BASE_DIV), \
SR(MILLISECOND_TIME_BASE_DIV), \
SR(DISPCLK_FREQ_CHANGE_CNTL), \
SR(RBBMIF_TIMEOUT_DIS), \
SR(RBBMIF_TIMEOUT_DIS_2), \
SR(DCHUBBUB_CRC_CTRL), \
SR(DPP_TOP0_DPP_CRC_CTRL), \
SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
SR(MPC_CRC_CTRL), \
SR(MPC_CRC_RESULT_GB), \
SR(MPC_CRC_RESULT_C), \
SR(MPC_CRC_RESULT_AR), \
SR(DOMAIN0_PG_CONFIG), \
SR(DOMAIN1_PG_CONFIG), \
SR(DOMAIN2_PG_CONFIG), \
SR(DOMAIN3_PG_CONFIG), \
SR(DOMAIN4_PG_CONFIG), \
SR(DOMAIN5_PG_CONFIG), \
SR(DOMAIN6_PG_CONFIG), \
SR(DOMAIN7_PG_CONFIG), \
SR(DOMAIN8_PG_CONFIG), \
SR(DOMAIN9_PG_CONFIG), \
SR(DOMAIN10_PG_CONFIG), \
SR(DOMAIN11_PG_CONFIG), \
SR(DOMAIN16_PG_CONFIG), \
SR(DOMAIN17_PG_CONFIG), \
SR(DOMAIN18_PG_CONFIG), \
SR(DOMAIN19_PG_CONFIG), \
SR(DOMAIN20_PG_CONFIG), \
SR(DOMAIN21_PG_CONFIG), \
SR(DOMAIN0_PG_STATUS), \
SR(DOMAIN1_PG_STATUS), \
SR(DOMAIN2_PG_STATUS), \
SR(DOMAIN3_PG_STATUS), \
SR(DOMAIN4_PG_STATUS), \
SR(DOMAIN5_PG_STATUS), \
SR(DOMAIN6_PG_STATUS), \
SR(DOMAIN7_PG_STATUS), \
SR(DOMAIN8_PG_STATUS), \
SR(DOMAIN9_PG_STATUS), \
SR(DOMAIN10_PG_STATUS), \
SR(DOMAIN11_PG_STATUS), \
SR(DOMAIN16_PG_STATUS), \
SR(DOMAIN17_PG_STATUS), \
SR(DOMAIN18_PG_STATUS), \
SR(DOMAIN19_PG_STATUS), \
SR(DOMAIN20_PG_STATUS), \
SR(DOMAIN21_PG_STATUS), \
SR(D1VGA_CONTROL), \
SR(D2VGA_CONTROL), \
SR(D3VGA_CONTROL), \
SR(D4VGA_CONTROL), \
SR(D5VGA_CONTROL), \
SR(D6VGA_CONTROL), \
SR(DC_IP_REQUEST_CNTL), \
BL_REG_LIST()
#endif
struct dce_hwseq_registers {
/* Backlight registers */
@ -453,6 +517,69 @@ struct dce_hwseq_registers {
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\
HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \
HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \
HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
#endif
#define HWSEQ_REG_FIELD_LIST(type) \
type DCFE_CLOCK_ENABLE; \
type DCFEV_CLOCK_ENABLE; \

42
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -666,7 +666,26 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
/* update AVI info frame (HDMI, DP)*/
/* TODO: FPGA may change to hwss.update_info_frame */
dce110_update_info_frame(pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL &&
pipe_ctx->plane_res.hubp != NULL) {
if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
/* if using dynamic meta, don't set up generic infopackets */
pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
pipe_ctx->stream_res.stream_enc,
true, pipe_ctx->plane_res.hubp->inst,
dc_is_dp_signal(pipe_ctx->stream->signal) ?
dmdata_dp : dmdata_hdmi);
} else
pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata(
pipe_ctx->stream_res.stream_enc,
false, pipe_ctx->plane_res.hubp->inst,
dc_is_dp_signal(pipe_ctx->stream->signal) ?
dmdata_dp : dmdata_hdmi);
}
#endif
/* enable early control to avoid corruption on DP monitor*/
active_total_with_borders =
@ -951,6 +970,10 @@ static void set_pme_wa_enable_by_version(struct dc *dc)
if (pp_smu) {
if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable)
pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx));
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
else if (pp_smu->ctx.ver == PP_SMU_VER_NV && pp_smu->nv_funcs.set_pme_wa_enable)
pp_smu->nv_funcs.set_pme_wa_enable(&(pp_smu->ctx));
#endif
}
}
@ -1337,6 +1360,9 @@ static enum dc_status apply_single_controller_ctx_to_hw(
struct dc_stream_state *stream = pipe_ctx->stream;
struct drr_params params = {0};
unsigned int event_triggers = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct pipe_ctx *odm_pipe = dc_res_get_odm_bottom_pipe(pipe_ctx);
#endif
if (dc->hwss.disable_stream_gating) {
dc->hwss.disable_stream_gating(dc, pipe_ctx);
@ -1402,6 +1428,20 @@ static enum dc_status apply_single_controller_ctx_to_hw(
pipe_ctx->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
if (odm_pipe) {
odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
odm_pipe->stream_res.opp,
COLOR_SPACE_YCBCR601,
stream->timing.display_color_depth,
stream->signal);
odm_pipe->stream_res.opp->funcs->opp_program_fmt(
odm_pipe->stream_res.opp,
&stream->bit_depth_params,
&stream->clamping);
}
#endif
if (!stream->dpms_off)
core_link_enable_stream(context, pipe_ctx);

13
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -49,6 +49,7 @@
#include "clk_mgr.h"
#define DC_LOGGER_INIT(logger)
#define CTX \
@ -346,6 +347,7 @@ void dcn10_log_hw_state(struct dc *dc,
}
DTN_INFO("\n");
DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
"dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
@ -1952,7 +1954,12 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
plane_state->format,
EXPANSION_MODE_ZERO,
plane_state->input_csc_color_matrix,
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
plane_state->color_space,
NULL);
#else
plane_state->color_space);
#endif
//set scale and bias registers
dcn10_build_prescale_params(&bns_params, plane_state);
@ -2406,6 +2413,12 @@ static void dcn10_apply_ctx_for_surface(
&pipe_ctx->ttu_regs);
}
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
/* Program secondary blending tree and writeback pipes */
if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree))
dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context);
#endif
if (interdependent_update)
lock_all_pipes(dc, context, false);
else

14
drivers/gpu/drm/amd/display/dc/dcn20/Makefile Normal file
View File

@ -0,0 +1,14 @@
#
# Makefile for DCN.
DCN20 = dcn20_resource.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o dcn20_hubp.o \
dcn20_mpc.o dcn20_opp.o dcn20_hubbub.o dcn20_optc.o dcn20_mmhubbub.o \
dcn20_stream_encoder.o dcn20_link_encoder.o dcn20_dccg.o \
dcn20_vmid.o dcn20_dwb.o dcn20_dwb_scl.o
CFLAGS_dcn20_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
AMD_DISPLAY_FILES += $(AMD_DAL_DCN20)

1926
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c Normal file
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90
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h Normal file
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@ -0,0 +1,90 @@
/*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_HWSS_DCN20_H__
#define __DC_HWSS_DCN20_H__
struct dc;
void dcn20_hw_sequencer_construct(struct dc *dc);
enum dc_status dcn20_enable_stream_timing(
struct pipe_ctx *pipe_ctx,
struct dc_state *context,
struct dc *dc);
void dcn20_blank_pixel_data(
struct dc *dc,
struct pipe_ctx *pipe_ctx,
bool blank);
void dcn20_program_output_csc(struct dc *dc,
struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
uint16_t *matrix,
int opp_id);
void dcn20_prepare_bandwidth(
struct dc *dc,
struct dc_state *context);
void dcn20_optimize_bandwidth(
struct dc *dc,
struct dc_state *context);
bool dcn20_update_bandwidth(
struct dc *dc,
struct dc_state *context);
void dcn20_disable_writeback(
struct dc *dc,
unsigned int dwb_pipe_inst);
bool dcn20_hwss_wait_for_blank_complete(
struct output_pixel_processor *opp);
bool dcn20_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
const struct dc_stream_state *stream);
bool dcn20_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
void dcn20_disable_stream(struct pipe_ctx *pipe_ctx, int option);
void dcn20_program_tripleBuffer(
const struct dc *dc,
struct pipe_ctx *pipe_ctx,
bool enableTripleBuffer);
void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx);
void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
struct pipe_ctx *pipe_ctx);
#endif /* __DC_HWSS_DCN20_H__ */

2741
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c Normal file
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134
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h Normal file
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@ -0,0 +1,134 @@
/*
* Copyright 2017 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_RESOURCE_DCN20_H__
#define __DC_RESOURCE_DCN20_H__
#include "core_types.h"
#define TO_DCN20_RES_POOL(pool)\
container_of(pool, struct dcn20_resource_pool, base)
struct dc;
struct resource_pool;
struct _vcs_dpi_display_pipe_params_st;
struct dcn20_resource_pool {
struct resource_pool base;
};
struct resource_pool *dcn20_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);
struct link_encoder *dcn20_link_encoder_create(
const struct encoder_init_data *enc_init_data);
unsigned int dcn20_calc_max_scaled_time(
unsigned int time_per_pixel,
enum mmhubbub_wbif_mode mode,
unsigned int urgent_watermark);
int dcn20_populate_dml_pipes_from_context(
struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
struct dc_state *state,
const struct resource_pool *pool,
struct dc_stream_state *stream);
void dcn20_populate_dml_writeback_from_context(
struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
struct stream_encoder *dcn20_stream_encoder_create(
enum engine_id eng_id,
struct dc_context *ctx);
struct dce_hwseq *dcn20_hwseq_create(
struct dc_context *ctx);
bool dcn20_get_dcc_compression_cap(const struct dc *dc,
const struct dc_dcc_surface_param *input,
struct dc_surface_dcc_cap *output);
void dcn20_dpp_destroy(struct dpp **dpp);
struct dpp *dcn20_dpp_create(
struct dc_context *ctx,
uint32_t inst);
struct input_pixel_processor *dcn20_ipp_create(
struct dc_context *ctx, uint32_t inst);
struct output_pixel_processor *dcn20_opp_create(
struct dc_context *ctx, uint32_t inst);
struct dce_aux *dcn20_aux_engine_create(
struct dc_context *ctx, uint32_t inst);
struct dce_i2c_hw *dcn20_i2c_hw_create(
struct dc_context *ctx,
uint32_t inst);
void dcn20_clock_source_destroy(struct clock_source **clk_src);
struct display_stream_compressor *dcn20_dsc_create(
struct dc_context *ctx, uint32_t inst);
void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx);
void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
struct hubp *dcn20_hubp_create(
struct dc_context *ctx,
uint32_t inst);
struct timing_generator *dcn20_timing_generator_create(
struct dc_context *ctx,
uint32_t instance);
struct mpc *dcn20_mpc_create(struct dc_context *ctx);
struct hubbub *dcn20_hubbub_create(struct dc_context *ctx);
bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool);
void dcn20_set_mcif_arb_params(
struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt);
bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context);
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);
enum dc_status dcn20_validate_global(struct dc *dc, struct dc_state *new_ctx);
enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);
void dcn20_patch_bounding_box(
struct dc *dc,
struct _vcs_dpi_soc_bounding_box_st *bb);
void dcn20_cap_soc_clocks(
struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table max_clocks);
#endif /* __DC_RESOURCE_DCN20_H__ */

46
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
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@ -65,11 +65,18 @@ struct dce_hwseq {
struct pipe_ctx;
struct dc_state;
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct dc_stream_status;
struct dc_writeback_info;
#endif
struct dchub_init_data;
struct dc_static_screen_events;
struct resource_pool;
struct resource_context;
struct stream_resource;
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
struct dc_addr_space_config;
#endif
struct hw_sequencer_funcs {
@ -102,6 +109,16 @@ struct hw_sequencer_funcs {
uint16_t *matrix,
int opp_id);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
void (*program_triplebuffer)(
const struct dc *dc,
struct pipe_ctx *pipe_ctx,
bool enableTripleBuffer);
void (*set_flip_control_gsl)(
struct pipe_ctx *pipe_ctx,
bool flip_immediate);
#endif
void (*update_plane_addr)(
const struct dc *dc,
struct pipe_ctx *pipe_ctx);
@ -114,6 +131,13 @@ struct hw_sequencer_funcs {
struct dce_hwseq *hws,
struct dchub_init_data *dh_data);
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
void (*init_dchub)(
struct dce_hwseq *hws,
struct dc *dc,
struct dc_addr_space_config *dh_data);
#endif
void (*update_mpcc)(
struct dc *dc,
struct pipe_ctx *pipe_ctx);
@ -197,6 +221,13 @@ struct hw_sequencer_funcs {
struct dc *dc,
struct dc_state *context);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
bool (*update_bandwidth)(
struct dc *dc,
struct dc_state *context);
bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx);
#endif
void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
int vmin, int vmax);
@ -241,6 +272,21 @@ struct hw_sequencer_funcs {
void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
void (*update_odm)(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
void (*program_all_writeback_pipes_in_tree)(
struct dc *dc,
const struct dc_stream_state *stream,
struct dc_state *context);
void (*update_writeback)(struct dc *dc,
const struct dc_stream_status *stream_status,
struct dc_writeback_info *wb_info);
void (*enable_writeback)(struct dc *dc,
const struct dc_stream_status *stream_status,
struct dc_writeback_info *wb_info);
void (*disable_writeback)(struct dc *dc,
unsigned int dwb_pipe_inst);
#endif
};
void color_space_to_black_color(

3
drivers/gpu/drm/amd/display/dc/inc/resource.h
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@ -44,6 +44,9 @@ struct resource_caps {
int num_pll;
int num_dwb;
int num_ddc;
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
int num_vmid;
#endif
};
struct resource_straps {