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drm/amdgpu: remove unneeded conversions to bool
Found with scripts/coccinelle/misc/boolconv.cocci. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c98b5c9714
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@ -5859,7 +5859,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
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bool enable = (state == AMD_PG_STATE_GATE);
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if (amdgpu_sriov_vf(adev))
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return 0;
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@ -6445,7 +6445,7 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
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case CHIP_CARRIZO:
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case CHIP_STONEY:
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gfx_v8_0_update_gfx_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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break;
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case CHIP_TONGA:
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gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
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@ -1520,9 +1520,9 @@ static int gmc_v8_0_set_clockgating_state(void *handle,
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switch (adev->asic_type) {
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case CHIP_FIJI:
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fiji_update_mc_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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fiji_update_mc_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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break;
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default:
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break;
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@ -1522,9 +1522,9 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
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case CHIP_CARRIZO:
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case CHIP_STONEY:
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sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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break;
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default:
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break;
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@ -1403,24 +1403,24 @@ static int vi_common_set_clockgating_state(void *handle,
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switch (adev->asic_type) {
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case CHIP_FIJI:
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vi_update_bif_medium_grain_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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vi_update_hdp_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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vi_update_hdp_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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vi_update_rom_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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break;
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case CHIP_CARRIZO:
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case CHIP_STONEY:
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vi_update_bif_medium_grain_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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vi_update_hdp_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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vi_update_hdp_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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vi_update_drm_light_sleep(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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state == AMD_CG_STATE_GATE);
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break;
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case CHIP_TONGA:
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case CHIP_POLARIS10:
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