mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 04:34:11 +08:00
Merge branch 'remotes/lorenzo/pci/endpoint'
- Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
endpoint framework (Wen Yang)
- Add interface to discover supported endpoint features to replace a
bitfield that wasn't flexible enough (Kishon Vijay Abraham I)
- Implement the new supported-feature interface for designware-plat,
dra7xx, rockchip, cadence (Kishon Vijay Abraham I)
- Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)
- Add layerscape endpoint mode support (Xiaowei Bao)
* remotes/lorenzo/pci/endpoint:
misc: pci_endpoint_test: Add the layerscape EP device support
PCI: layerscape: Add EP mode support
arm64: dts: Add the PCIE EP node in dts
dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
PCI: endpoint: Remove features member in struct pci_epc
PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
PCI: pci-epf-test: Remove setting epf_bar flags in function driver
PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
PCI: endpoint: Add helper to get first unreserved BAR
PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
PCI: endpoint: Add new pci_epc_ops to get EPC features
PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
This commit is contained in:
Bjorn Helgaas
commit
7e5b22ddb2
@ -13,6 +13,7 @@ information.
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Required properties:
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- compatible: should contain the platform identifier such as:
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RC mode:
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"fsl,ls1021a-pcie"
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"fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
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"fsl,ls2088a-pcie"
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@ -20,6 +21,8 @@ Required properties:
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"fsl,ls1046a-pcie"
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"fsl,ls1043a-pcie"
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"fsl,ls1012a-pcie"
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EP mode:
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"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
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- reg: base addresses and lengths of the PCIe controller register blocks.
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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@ -657,6 +657,17 @@
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status = "disabled";
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};
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pcie_ep@3400000 {
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compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
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reg = <0x00 0x03400000 0x0 0x00100000
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0x40 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ib-windows = <6>;
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num-ob-windows = <8>;
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num-lanes = <2>;
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status = "disabled";
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};
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pcie@3500000 {
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compatible = "fsl,ls1046a-pcie";
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reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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@ -683,6 +694,17 @@
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status = "disabled";
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};
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pcie_ep@3500000 {
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compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
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reg = <0x00 0x03500000 0x0 0x00100000
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0x48 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ib-windows = <6>;
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num-ob-windows = <8>;
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num-lanes = <2>;
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status = "disabled";
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};
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pcie@3600000 {
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compatible = "fsl,ls1046a-pcie";
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reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
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@ -709,6 +731,17 @@
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status = "disabled";
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};
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pcie_ep@3600000 {
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compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
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reg = <0x00 0x03600000 0x0 0x00100000
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0x50 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ib-windows = <6>;
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num-ob-windows = <8>;
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num-lanes = <2>;
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status = "disabled";
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};
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qdma: dma-controller@8380000 {
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compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
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reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
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@ -729,7 +762,6 @@
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queue-sizes = <64 64>;
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big-endian;
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};
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};
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reserved-memory {
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@ -788,6 +788,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
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static const struct pci_device_id pci_endpoint_test_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
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{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
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{ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
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{ }
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};
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@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
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obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
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obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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@ -394,9 +394,22 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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return 0;
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}
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static const struct pci_epc_features dra7xx_pcie_epc_features = {
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.linkup_notifier = true,
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.msi_capable = true,
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.msix_capable = false,
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};
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static const struct pci_epc_features*
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dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
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{
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return &dra7xx_pcie_epc_features;
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}
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static struct dw_pcie_ep_ops pcie_ep_ops = {
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.ep_init = dra7xx_pcie_ep_init,
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.raise_irq = dra7xx_pcie_raise_irq,
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.get_features = dra7xx_pcie_get_features,
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};
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static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
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156
drivers/pci/controller/dwc/pci-layerscape-ep.c
Normal file
156
drivers/pci/controller/dwc/pci-layerscape-ep.c
Normal file
@ -0,0 +1,156 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe controller EP driver for Freescale Layerscape SoCs
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*
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* Copyright (C) 2018 NXP Semiconductor.
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*
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* Author: Xiaowei Bao <xiaowei.bao@nxp.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include "pcie-designware.h"
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#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
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struct ls_pcie_ep {
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struct dw_pcie *pci;
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};
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#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
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static int ls_pcie_establish_link(struct dw_pcie *pci)
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{
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return 0;
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}
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static const struct dw_pcie_ops ls_pcie_ep_ops = {
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.start_link = ls_pcie_establish_link,
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};
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static const struct of_device_id ls_pcie_ep_of_match[] = {
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{ .compatible = "fsl,ls-pcie-ep",},
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{ },
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};
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static const struct pci_epc_features ls_pcie_epc_features = {
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.linkup_notifier = false,
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.msi_capable = true,
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.msix_capable = false,
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};
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static const struct pci_epc_features*
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ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
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{
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return &ls_pcie_epc_features;
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}
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static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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enum pci_barno bar;
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for (bar = BAR_0; bar <= BAR_5; bar++)
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dw_pcie_ep_reset_bar(pci, bar);
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}
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static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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enum pci_epc_irq_type type, u16 interrupt_num)
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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switch (type) {
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case PCI_EPC_IRQ_LEGACY:
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return dw_pcie_ep_raise_legacy_irq(ep, func_no);
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case PCI_EPC_IRQ_MSI:
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return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
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case PCI_EPC_IRQ_MSIX:
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return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
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default:
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dev_err(pci->dev, "UNKNOWN IRQ type\n");
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return -EINVAL;
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}
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}
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static struct dw_pcie_ep_ops pcie_ep_ops = {
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.ep_init = ls_pcie_ep_init,
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.raise_irq = ls_pcie_ep_raise_irq,
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.get_features = ls_pcie_ep_get_features,
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};
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static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
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struct platform_device *pdev)
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{
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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struct dw_pcie_ep *ep;
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struct resource *res;
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int ret;
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ep = &pci->ep;
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ep->ops = &pcie_ep_ops;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
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if (!res)
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return -EINVAL;
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ep->phys_base = res->start;
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ep->addr_size = resource_size(res);
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ret = dw_pcie_ep_init(ep);
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if (ret) {
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dev_err(dev, "failed to initialize endpoint\n");
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return ret;
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}
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return 0;
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}
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static int __init ls_pcie_ep_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct ls_pcie_ep *pcie;
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struct resource *dbi_base;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
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if (IS_ERR(pci->dbi_base))
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return PTR_ERR(pci->dbi_base);
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pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
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pci->dev = dev;
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pci->ops = &ls_pcie_ep_ops;
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pcie->pci = pci;
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platform_set_drvdata(pdev, pcie);
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ret = ls_add_pcie_ep(pcie, pdev);
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return ret;
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}
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static struct platform_driver ls_pcie_ep_driver = {
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.driver = {
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.name = "layerscape-pcie-ep",
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.of_match_table = ls_pcie_ep_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
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@ -355,6 +355,17 @@ static int dw_pcie_ep_start(struct pci_epc *epc)
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return pci->ops->start_link(pci);
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}
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static const struct pci_epc_features*
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dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
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{
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struct dw_pcie_ep *ep = epc_get_drvdata(epc);
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if (!ep->ops->get_features)
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return NULL;
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return ep->ops->get_features(ep);
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}
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static const struct pci_epc_ops epc_ops = {
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.write_header = dw_pcie_ep_write_header,
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.set_bar = dw_pcie_ep_set_bar,
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@ -368,6 +379,7 @@ static const struct pci_epc_ops epc_ops = {
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.raise_irq = dw_pcie_ep_raise_irq,
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.start = dw_pcie_ep_start,
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.stop = dw_pcie_ep_stop,
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.get_features = dw_pcie_ep_get_features,
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};
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int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
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@ -68,14 +68,10 @@ static const struct dw_pcie_ops dw_pcie_ops = {
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static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
|
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{
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struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
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struct pci_epc *epc = ep->epc;
|
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enum pci_barno bar;
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|
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for (bar = BAR_0; bar <= BAR_5; bar++)
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dw_pcie_ep_reset_bar(pci, bar);
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epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
|
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epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
|
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}
|
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|
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static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
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@ -98,9 +94,22 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
|
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return 0;
|
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}
|
||||
|
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static const struct pci_epc_features dw_plat_pcie_epc_features = {
|
||||
.linkup_notifier = false,
|
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.msi_capable = true,
|
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.msix_capable = true,
|
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};
|
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|
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static const struct pci_epc_features*
|
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dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
|
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{
|
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return &dw_plat_pcie_epc_features;
|
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}
|
||||
|
||||
static struct dw_pcie_ep_ops pcie_ep_ops = {
|
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.ep_init = dw_plat_pcie_ep_init,
|
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.raise_irq = dw_plat_pcie_ep_raise_irq,
|
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.get_features = dw_plat_pcie_get_features,
|
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};
|
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|
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static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
|
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|
||||
@ -195,6 +195,7 @@ struct dw_pcie_ep_ops {
|
||||
void (*ep_init)(struct dw_pcie_ep *ep);
|
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int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
|
||||
enum pci_epc_irq_type type, u16 interrupt_num);
|
||||
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
|
||||
};
|
||||
|
||||
struct dw_pcie_ep {
|
||||
|
||||
@ -396,21 +396,21 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
|
||||
cfg |= BIT(epf->func_no);
|
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
|
||||
|
||||
/*
|
||||
* The PCIe links are automatically established by the controller
|
||||
* once for all at powerup: the software can neither start nor stop
|
||||
* those links later at runtime.
|
||||
*
|
||||
* Then we only have to notify the EP core that our links are already
|
||||
* established. However we don't call directly pci_epc_linkup() because
|
||||
* we've already locked the epc->lock.
|
||||
*/
|
||||
list_for_each_entry(epf, &epc->pci_epf, list)
|
||||
pci_epf_linkup(epf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pci_epc_features cdns_pcie_epc_features = {
|
||||
.linkup_notifier = false,
|
||||
.msi_capable = true,
|
||||
.msix_capable = false,
|
||||
};
|
||||
|
||||
static const struct pci_epc_features*
|
||||
cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
|
||||
{
|
||||
return &cdns_pcie_epc_features;
|
||||
}
|
||||
|
||||
static const struct pci_epc_ops cdns_pcie_epc_ops = {
|
||||
.write_header = cdns_pcie_ep_write_header,
|
||||
.set_bar = cdns_pcie_ep_set_bar,
|
||||
@ -421,6 +421,7 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = {
|
||||
.get_msi = cdns_pcie_ep_get_msi,
|
||||
.raise_irq = cdns_pcie_ep_raise_irq,
|
||||
.start = cdns_pcie_ep_start,
|
||||
.get_features = cdns_pcie_ep_get_features,
|
||||
};
|
||||
|
||||
static const struct of_device_id cdns_pcie_ep_of_match[] = {
|
||||
|
||||
@ -499,12 +499,21 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc)
|
||||
|
||||
rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
|
||||
|
||||
list_for_each_entry(epf, &epc->pci_epf, list)
|
||||
pci_epf_linkup(epf);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pci_epc_features rockchip_pcie_epc_features = {
|
||||
.linkup_notifier = false,
|
||||
.msi_capable = true,
|
||||
.msix_capable = false,
|
||||
};
|
||||
|
||||
static const struct pci_epc_features*
|
||||
rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
|
||||
{
|
||||
return &rockchip_pcie_epc_features;
|
||||
}
|
||||
|
||||
static const struct pci_epc_ops rockchip_pcie_epc_ops = {
|
||||
.write_header = rockchip_pcie_ep_write_header,
|
||||
.set_bar = rockchip_pcie_ep_set_bar,
|
||||
@ -515,6 +524,7 @@ static const struct pci_epc_ops rockchip_pcie_epc_ops = {
|
||||
.get_msi = rockchip_pcie_ep_get_msi,
|
||||
.raise_irq = rockchip_pcie_ep_raise_irq,
|
||||
.start = rockchip_pcie_ep_start,
|
||||
.get_features = rockchip_pcie_ep_get_features,
|
||||
};
|
||||
|
||||
static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
|
||||
|
||||
@ -47,9 +47,8 @@ struct pci_epf_test {
|
||||
void *reg[6];
|
||||
struct pci_epf *epf;
|
||||
enum pci_barno test_reg_bar;
|
||||
bool linkup_notifier;
|
||||
bool msix_available;
|
||||
struct delayed_work cmd_handler;
|
||||
const struct pci_epc_features *epc_features;
|
||||
};
|
||||
|
||||
struct pci_epf_test_reg {
|
||||
@ -71,11 +70,6 @@ static struct pci_epf_header test_header = {
|
||||
.interrupt_pin = PCI_INTERRUPT_INTA,
|
||||
};
|
||||
|
||||
struct pci_epf_test_data {
|
||||
enum pci_barno test_reg_bar;
|
||||
bool linkup_notifier;
|
||||
};
|
||||
|
||||
static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
|
||||
|
||||
static int pci_epf_test_copy(struct pci_epf_test *epf_test)
|
||||
@ -175,7 +169,7 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
|
||||
goto err_map_addr;
|
||||
}
|
||||
|
||||
memcpy(buf, src_addr, reg->size);
|
||||
memcpy_fromio(buf, src_addr, reg->size);
|
||||
|
||||
crc32 = crc32_le(~0, buf, reg->size);
|
||||
if (crc32 != reg->checksum)
|
||||
@ -230,7 +224,7 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
|
||||
get_random_bytes(buf, reg->size);
|
||||
reg->checksum = crc32_le(~0, buf, reg->size);
|
||||
|
||||
memcpy(dst_addr, buf, reg->size);
|
||||
memcpy_toio(dst_addr, buf, reg->size);
|
||||
|
||||
/*
|
||||
* wait 1ms inorder for the write to complete. Without this delay L3
|
||||
@ -402,13 +396,15 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
|
||||
struct device *dev = &epf->dev;
|
||||
struct pci_epf_test *epf_test = epf_get_drvdata(epf);
|
||||
enum pci_barno test_reg_bar = epf_test->test_reg_bar;
|
||||
const struct pci_epc_features *epc_features;
|
||||
|
||||
epc_features = epf_test->epc_features;
|
||||
|
||||
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
||||
epf_bar = &epf->bar[bar];
|
||||
|
||||
epf_bar->flags |= upper_32_bits(epf_bar->size) ?
|
||||
PCI_BASE_ADDRESS_MEM_TYPE_64 :
|
||||
PCI_BASE_ADDRESS_MEM_TYPE_32;
|
||||
if (!!(epc_features->reserved_bar & (1 << bar)))
|
||||
continue;
|
||||
|
||||
ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);
|
||||
if (ret) {
|
||||
@ -433,9 +429,13 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
|
||||
{
|
||||
struct pci_epf_test *epf_test = epf_get_drvdata(epf);
|
||||
struct device *dev = &epf->dev;
|
||||
struct pci_epf_bar *epf_bar;
|
||||
void *base;
|
||||
int bar;
|
||||
enum pci_barno test_reg_bar = epf_test->test_reg_bar;
|
||||
const struct pci_epc_features *epc_features;
|
||||
|
||||
epc_features = epf_test->epc_features;
|
||||
|
||||
base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
|
||||
test_reg_bar);
|
||||
@ -446,37 +446,69 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
|
||||
epf_test->reg[test_reg_bar] = base;
|
||||
|
||||
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
||||
epf_bar = &epf->bar[bar];
|
||||
if (bar == test_reg_bar)
|
||||
continue;
|
||||
|
||||
if (!!(epc_features->reserved_bar & (1 << bar)))
|
||||
continue;
|
||||
|
||||
base = pci_epf_alloc_space(epf, bar_size[bar], bar);
|
||||
if (!base)
|
||||
dev_err(dev, "Failed to allocate space for BAR%d\n",
|
||||
bar);
|
||||
epf_test->reg[bar] = base;
|
||||
if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
|
||||
bar++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pci_epf_configure_bar(struct pci_epf *epf,
|
||||
const struct pci_epc_features *epc_features)
|
||||
{
|
||||
struct pci_epf_bar *epf_bar;
|
||||
bool bar_fixed_64bit;
|
||||
int i;
|
||||
|
||||
for (i = BAR_0; i <= BAR_5; i++) {
|
||||
epf_bar = &epf->bar[i];
|
||||
bar_fixed_64bit = !!(epc_features->bar_fixed_64bit & (1 << i));
|
||||
if (bar_fixed_64bit)
|
||||
epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
|
||||
if (epc_features->bar_fixed_size[i])
|
||||
bar_size[i] = epc_features->bar_fixed_size[i];
|
||||
}
|
||||
}
|
||||
|
||||
static int pci_epf_test_bind(struct pci_epf *epf)
|
||||
{
|
||||
int ret;
|
||||
struct pci_epf_test *epf_test = epf_get_drvdata(epf);
|
||||
struct pci_epf_header *header = epf->header;
|
||||
const struct pci_epc_features *epc_features;
|
||||
enum pci_barno test_reg_bar = BAR_0;
|
||||
struct pci_epc *epc = epf->epc;
|
||||
struct device *dev = &epf->dev;
|
||||
bool linkup_notifier = false;
|
||||
bool msix_capable = false;
|
||||
bool msi_capable = true;
|
||||
|
||||
if (WARN_ON_ONCE(!epc))
|
||||
return -EINVAL;
|
||||
|
||||
if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
|
||||
epf_test->linkup_notifier = false;
|
||||
else
|
||||
epf_test->linkup_notifier = true;
|
||||
epc_features = pci_epc_get_features(epc, epf->func_no);
|
||||
if (epc_features) {
|
||||
linkup_notifier = epc_features->linkup_notifier;
|
||||
msix_capable = epc_features->msix_capable;
|
||||
msi_capable = epc_features->msi_capable;
|
||||
test_reg_bar = pci_epc_get_first_free_bar(epc_features);
|
||||
pci_epf_configure_bar(epf, epc_features);
|
||||
}
|
||||
|
||||
epf_test->msix_available = epc->features & EPC_FEATURE_MSIX_AVAILABLE;
|
||||
|
||||
epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features);
|
||||
epf_test->test_reg_bar = test_reg_bar;
|
||||
epf_test->epc_features = epc_features;
|
||||
|
||||
ret = pci_epc_write_header(epc, epf->func_no, header);
|
||||
if (ret) {
|
||||
@ -492,13 +524,15 @@ static int pci_epf_test_bind(struct pci_epf *epf)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (msi_capable) {
|
||||
ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
|
||||
if (ret) {
|
||||
dev_err(dev, "MSI configuration failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (epf_test->msix_available) {
|
||||
if (msix_capable) {
|
||||
ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
|
||||
if (ret) {
|
||||
dev_err(dev, "MSI-X configuration failed\n");
|
||||
@ -506,7 +540,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
|
||||
}
|
||||
}
|
||||
|
||||
if (!epf_test->linkup_notifier)
|
||||
if (!linkup_notifier)
|
||||
queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
|
||||
|
||||
return 0;
|
||||
@ -523,17 +557,6 @@ static int pci_epf_test_probe(struct pci_epf *epf)
|
||||
{
|
||||
struct pci_epf_test *epf_test;
|
||||
struct device *dev = &epf->dev;
|
||||
const struct pci_epf_device_id *match;
|
||||
struct pci_epf_test_data *data;
|
||||
enum pci_barno test_reg_bar = BAR_0;
|
||||
bool linkup_notifier = true;
|
||||
|
||||
match = pci_epf_match_device(pci_epf_test_ids, epf);
|
||||
data = (struct pci_epf_test_data *)match->driver_data;
|
||||
if (data) {
|
||||
test_reg_bar = data->test_reg_bar;
|
||||
linkup_notifier = data->linkup_notifier;
|
||||
}
|
||||
|
||||
epf_test = devm_kzalloc(dev, sizeof(*epf_test), GFP_KERNEL);
|
||||
if (!epf_test)
|
||||
@ -541,8 +564,6 @@ static int pci_epf_test_probe(struct pci_epf *epf)
|
||||
|
||||
epf->header = &test_header;
|
||||
epf_test->epf = epf;
|
||||
epf_test->test_reg_bar = test_reg_bar;
|
||||
epf_test->linkup_notifier = linkup_notifier;
|
||||
|
||||
INIT_DELAYED_WORK(&epf_test->cmd_handler, pci_epf_test_cmd_handler);
|
||||
|
||||
|
||||
@ -83,6 +83,59 @@ err:
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_epc_get);
|
||||
|
||||
/**
|
||||
* pci_epc_get_first_free_bar() - helper to get first unreserved BAR
|
||||
* @epc_features: pci_epc_features structure that holds the reserved bar bitmap
|
||||
*
|
||||
* Invoke to get the first unreserved BAR that can be used for endpoint
|
||||
* function. For any incorrect value in reserved_bar return '0'.
|
||||
*/
|
||||
unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
|
||||
*epc_features)
|
||||
{
|
||||
int free_bar;
|
||||
|
||||
if (!epc_features)
|
||||
return 0;
|
||||
|
||||
free_bar = ffz(epc_features->reserved_bar);
|
||||
if (free_bar > 5)
|
||||
return 0;
|
||||
|
||||
return free_bar;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar);
|
||||
|
||||
/**
|
||||
* pci_epc_get_features() - get the features supported by EPC
|
||||
* @epc: the features supported by *this* EPC device will be returned
|
||||
* @func_no: the features supported by the EPC device specific to the
|
||||
* endpoint function with func_no will be returned
|
||||
*
|
||||
* Invoke to get the features provided by the EPC which may be
|
||||
* specific to an endpoint function. Returns pci_epc_features on success
|
||||
* and NULL for any failures.
|
||||
*/
|
||||
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
|
||||
u8 func_no)
|
||||
{
|
||||
const struct pci_epc_features *epc_features;
|
||||
unsigned long flags;
|
||||
|
||||
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
|
||||
return NULL;
|
||||
|
||||
if (!epc->ops->get_features)
|
||||
return NULL;
|
||||
|
||||
spin_lock_irqsave(&epc->lock, flags);
|
||||
epc_features = epc->ops->get_features(epc, func_no);
|
||||
spin_unlock_irqrestore(&epc->lock, flags);
|
||||
|
||||
return epc_features;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_epc_get_features);
|
||||
|
||||
/**
|
||||
* pci_epc_stop() - stop the PCI link
|
||||
* @epc: the link of the EPC device that has to be stopped
|
||||
|
||||
@ -131,7 +131,9 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
|
||||
epf->bar[bar].phys_addr = phys_addr;
|
||||
epf->bar[bar].size = size;
|
||||
epf->bar[bar].barno = bar;
|
||||
epf->bar[bar].flags = PCI_BASE_ADDRESS_SPACE_MEMORY;
|
||||
epf->bar[bar].flags |= upper_32_bits(size) ?
|
||||
PCI_BASE_ADDRESS_MEM_TYPE_64 :
|
||||
PCI_BASE_ADDRESS_MEM_TYPE_32;
|
||||
|
||||
return space;
|
||||
}
|
||||
|
||||
@ -59,6 +59,8 @@ struct pci_epc_ops {
|
||||
enum pci_epc_irq_type type, u16 interrupt_num);
|
||||
int (*start)(struct pci_epc *epc);
|
||||
void (*stop)(struct pci_epc *epc);
|
||||
const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
|
||||
u8 func_no);
|
||||
struct module *owner;
|
||||
};
|
||||
|
||||
@ -97,16 +99,25 @@ struct pci_epc {
|
||||
struct config_group *group;
|
||||
/* spinlock to protect against concurrent access of EP controller */
|
||||
spinlock_t lock;
|
||||
unsigned int features;
|
||||
};
|
||||
|
||||
#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0)
|
||||
#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3))
|
||||
#define EPC_FEATURE_MSIX_AVAILABLE BIT(4)
|
||||
#define EPC_FEATURE_SET_BAR(features, bar) \
|
||||
(features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
|
||||
#define EPC_FEATURE_GET_BAR(features) \
|
||||
((features & EPC_FEATURE_BAR_MASK) >> 1)
|
||||
/**
|
||||
* struct pci_epc_features - features supported by a EPC device per function
|
||||
* @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
|
||||
* @msi_capable: indicate if the endpoint function has MSI capability
|
||||
* @msix_capable: indicate if the endpoint function has MSI-X capability
|
||||
* @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
|
||||
* @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
|
||||
* @bar_fixed_size: Array specifying the size supported by each BAR
|
||||
*/
|
||||
struct pci_epc_features {
|
||||
unsigned int linkup_notifier : 1;
|
||||
unsigned int msi_capable : 1;
|
||||
unsigned int msix_capable : 1;
|
||||
u8 reserved_bar;
|
||||
u8 bar_fixed_64bit;
|
||||
u64 bar_fixed_size[BAR_5 + 1];
|
||||
};
|
||||
|
||||
#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
|
||||
|
||||
@ -158,6 +169,10 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
|
||||
enum pci_epc_irq_type type, u16 interrupt_num);
|
||||
int pci_epc_start(struct pci_epc *epc);
|
||||
void pci_epc_stop(struct pci_epc *epc);
|
||||
const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
|
||||
u8 func_no);
|
||||
unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
|
||||
*epc_features);
|
||||
struct pci_epc *pci_epc_get(const char *epc_name);
|
||||
void pci_epc_put(struct pci_epc *epc);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user