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ARM: EXYNOS: Add PMU table for EXYNOS5250
This patch adds pmu table setting feature for EXYNOS5250. Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> [kgene.kim@samsung.com: re-worked on top of v3.4-rc7] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Jongpill Lee
Kukjin Kim
parent
c9347101d8
commit
7d44d2ba1a
@ -22,7 +22,7 @@ obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
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obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_ARCH_EXYNOS4) += pmu.o
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obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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@ -113,7 +113,7 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
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exynos4_set_wakeupmask();
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exynos4_set_wakeupmask();
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/* Set value of power down register for aftr mode */
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/* Set value of power down register for aftr mode */
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exynos4_sys_powerdown_conf(SYS_AFTR);
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exynos_sys_powerdown_conf(SYS_AFTR);
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__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
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__raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
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__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
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__raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
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@ -23,12 +23,12 @@ enum sys_powerdown {
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};
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};
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extern unsigned long l2x0_regs_phys;
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extern unsigned long l2x0_regs_phys;
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struct exynos4_pmu_conf {
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struct exynos_pmu_conf {
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void __iomem *reg;
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void __iomem *reg;
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unsigned int val[NUM_SYS_POWERDOWN];
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unsigned int val[NUM_SYS_POWERDOWN];
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};
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};
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extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
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extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
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extern void s3c_cpu_resume(void);
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extern void s3c_cpu_resume(void);
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#endif /* __ASM_ARCH_PMU_H */
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#endif /* __ASM_ARCH_PMU_H */
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@ -1,9 +1,8 @@
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/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
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/*
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*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* http://www.samsung.com
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*
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*
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* EXYNOS4 - Power management unit definition
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* EXYNOS - Power management unit definition
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* it under the terms of the GNU General Public License version 2 as
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@ -226,4 +225,138 @@
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#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
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#define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034)
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#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
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#define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038)
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/* For EXYNOS5 */
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#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
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#define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000)
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#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004)
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#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008)
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#define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010)
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#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014)
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#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018)
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#define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040)
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#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048)
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#define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050)
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#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054)
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#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058)
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#define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080)
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#define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0)
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#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100)
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#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104)
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#define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C)
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#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120)
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#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124)
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#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C)
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#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130)
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#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134)
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#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138)
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#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140)
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#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144)
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#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148)
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#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C)
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#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150)
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#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154)
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#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164)
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#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170)
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#define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180)
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#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184)
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#define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188)
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#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190)
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#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194)
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#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198)
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#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0)
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#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4)
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#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0)
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#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4)
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#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0)
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#define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8)
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#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC)
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#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0)
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#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4)
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#define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8)
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#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC)
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#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0)
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#define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4)
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#define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8)
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#define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC)
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#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4)
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#define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC)
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#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200)
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#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204)
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#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208)
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#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220)
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#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224)
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#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228)
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#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C)
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#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230)
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#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234)
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#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238)
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#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C)
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#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240)
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#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250)
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#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260)
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#define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280)
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#define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284)
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#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0)
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#define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300)
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#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320)
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#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340)
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#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344)
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#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348)
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#define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400)
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#define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404)
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#define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408)
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#define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C)
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#define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414)
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#define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418)
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#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480)
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#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484)
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#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488)
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#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C)
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#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494)
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#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498)
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#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0)
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#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4)
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#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8)
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#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC)
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#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4)
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#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8)
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#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580)
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#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584)
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#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588)
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#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C)
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#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594)
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#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598)
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#define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
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#define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
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#define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208)
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#define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288)
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#define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
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#define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
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#define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8)
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#define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48)
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#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004)
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#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024)
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#define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008)
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#define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028)
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#define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048)
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#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060)
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#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064)
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#define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068)
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#define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8)
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#define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8)
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#define EXYNOS5_USE_SC_FEEDBACK (1 << 1)
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#define EXYNOS5_USE_SC_COUNTER (1 << 0)
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#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2)
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#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7)
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#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24)
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#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16)
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#define EXYNOS5_OPTION_USE_RETENTION (1 << 4)
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#endif /* __ASM_ARCH_REGS_PMU_H */
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#endif /* __ASM_ARCH_REGS_PMU_H */
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@ -98,7 +98,7 @@ static void exynos_pm_prepare(void)
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/* Set value of power down register for sleep mode */
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/* Set value of power down register for sleep mode */
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exynos4_sys_powerdown_conf(SYS_SLEEP);
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exynos_sys_powerdown_conf(SYS_SLEEP);
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__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
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/* ensure at least INFORM0 has the resume address */
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/* ensure at least INFORM0 has the resume address */
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/* linux/arch/arm/mach-exynos4/pmu.c
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/*
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*
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* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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* http://www.samsung.com/
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*
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*
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* EXYNOS4210 - CPU PMU(Power Management Unit) support
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* EXYNOS - CPU PMU(Power Management Unit) support
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* it under the terms of the GNU General Public License version 2 as
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@ -16,9 +15,9 @@
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#include <mach/regs-clock.h>
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#include <mach/regs-clock.h>
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#include <mach/pmu.h>
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#include <mach/pmu.h>
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static struct exynos4_pmu_conf *exynos4_pmu_config;
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static struct exynos_pmu_conf *exynos_pmu_config;
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|
||||||
static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
|
static struct exynos_pmu_conf exynos4210_pmu_config[] = {
|
||||||
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
||||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
||||||
@ -94,7 +93,7 @@ static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
|
|||||||
{ PMU_TABLE_END,},
|
{ PMU_TABLE_END,},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
|
static struct exynos_pmu_conf exynos4x12_pmu_config[] = {
|
||||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
||||||
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
||||||
@ -202,7 +201,7 @@ static struct exynos4_pmu_conf exynos4x12_pmu_config[] = {
|
|||||||
{ PMU_TABLE_END,},
|
{ PMU_TABLE_END,},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
|
static struct exynos_pmu_conf exynos4412_pmu_config[] = {
|
||||||
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
|
{ S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||||
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
|
{ S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } },
|
||||||
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
|
{ S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } },
|
||||||
@ -212,13 +211,116 @@ static struct exynos4_pmu_conf exynos4412_pmu_config[] = {
|
|||||||
{ PMU_TABLE_END,},
|
{ PMU_TABLE_END,},
|
||||||
};
|
};
|
||||||
|
|
||||||
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
|
static struct exynos_pmu_conf exynos5250_pmu_config[] = {
|
||||||
|
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
||||||
|
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
||||||
|
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
||||||
|
{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||||
|
{ EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
||||||
|
{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
|
||||||
|
{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||||
|
{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||||
|
{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||||
|
{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
||||||
|
{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
||||||
|
{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||||
|
{ EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
||||||
|
{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
||||||
|
{ EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
||||||
|
{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
||||||
|
{ PMU_TABLE_END,},
|
||||||
|
};
|
||||||
|
|
||||||
|
void exynos_sys_powerdown_conf(enum sys_powerdown mode)
|
||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
|
|
||||||
for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
|
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
|
||||||
__raw_writel(exynos4_pmu_config[i].val[mode],
|
__raw_writel(exynos_pmu_config[i].val[mode],
|
||||||
exynos4_pmu_config[i].reg);
|
exynos_pmu_config[i].reg);
|
||||||
|
|
||||||
if (soc_is_exynos4412()) {
|
if (soc_is_exynos4412()) {
|
||||||
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
|
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
|
||||||
@ -227,20 +329,23 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static int __init exynos4_pmu_init(void)
|
static int __init exynos_pmu_init(void)
|
||||||
{
|
{
|
||||||
exynos4_pmu_config = exynos4210_pmu_config;
|
exynos_pmu_config = exynos4210_pmu_config;
|
||||||
|
|
||||||
if (soc_is_exynos4210()) {
|
if (soc_is_exynos4210()) {
|
||||||
exynos4_pmu_config = exynos4210_pmu_config;
|
exynos_pmu_config = exynos4210_pmu_config;
|
||||||
pr_info("EXYNOS4210 PMU Initialize\n");
|
pr_info("EXYNOS4210 PMU Initialize\n");
|
||||||
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||||
exynos4_pmu_config = exynos4x12_pmu_config;
|
exynos_pmu_config = exynos4x12_pmu_config;
|
||||||
pr_info("EXYNOS4x12 PMU Initialize\n");
|
pr_info("EXYNOS4x12 PMU Initialize\n");
|
||||||
|
} else if (soc_is_exynos5250()) {
|
||||||
|
exynos_pmu_config = exynos5250_pmu_config;
|
||||||
|
pr_info("EXYNOS5250 PMU Initialize\n");
|
||||||
} else {
|
} else {
|
||||||
pr_info("EXYNOS4: PMU not supported\n");
|
pr_info("EXYNOS: PMU not supported\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
arch_initcall(exynos4_pmu_init);
|
arch_initcall(exynos_pmu_init);
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user