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https://github.com/edk2-porting/linux-next.git
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ARM: SAMSUNG: Remove pwm-clock infrastructure
Since all the used PWM prescalers and dividers configuration has been moved to appropriate drivers, the pwm-clock infrastructure is now unused and so this patch removes it. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mark Brown <broonie@linaro.org> Tested-by: Sylwester Nawrocki <sylvester.nawrocki@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Tomasz Figa
parent
a2eed492f8
commit
7c93c200f6
@ -281,6 +281,5 @@ int __init s3c2410_baseclk_add(void)
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(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
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(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
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s3c_pwmclk_init();
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return 0;
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}
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@ -757,6 +757,5 @@ int __init s3c2412_baseclk_add(void)
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}
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clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
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s3c_pwmclk_init();
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return 0;
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}
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@ -168,6 +168,4 @@ void __init s3c2416_init_clocks(int xtal)
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s3c24xx_register_clock(&hsmmc0_clk);
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clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
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s3c_pwmclk_init();
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}
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@ -209,6 +209,4 @@ void __init s3c2443_init_clocks(int xtal)
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s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
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clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
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s3c_pwmclk_init();
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}
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@ -1004,6 +1004,4 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
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for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
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s3c_register_clksrc(clksrc_cdev[cnt], 1);
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clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
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s3c_pwmclk_init();
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}
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@ -629,6 +629,4 @@ void __init s5p6440_register_clocks(void)
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clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
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s3c24xx_register_clock(&dummy_apb_pclk);
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s3c_pwmclk_init();
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}
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@ -698,6 +698,4 @@ void __init s5p6450_register_clocks(void)
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clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
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s3c24xx_register_clock(&dummy_apb_pclk);
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s3c_pwmclk_init();
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}
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@ -1358,6 +1358,4 @@ void __init s5pc100_register_clocks(void)
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s3c_disable_clocks(clk_cdev[ptr], 1);
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s3c24xx_register_clock(&dummy_apb_pclk);
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s3c_pwmclk_init();
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}
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@ -1362,5 +1362,4 @@ void __init s5pv210_register_clocks(void)
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for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
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s3c_disable_clocks(clk_cdev[ptr], 1);
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s3c_pwmclk_init();
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}
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@ -14,7 +14,6 @@ obj- :=
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obj-y += init.o cpu.o
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obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
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obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o
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obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
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obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
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@ -145,10 +145,6 @@ extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
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extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
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/* Init for pwm clock code */
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extern void s3c_pwmclk_init(void);
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/* Global watchdog clock used by arch_wtd_reset() callback */
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extern struct clk *s3c2410_wdtclk;
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@ -1,81 +0,0 @@
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/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* SAMSUNG - pwm clock and timer support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PLAT_PWM_CLOCK_H
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#define __ASM_PLAT_PWM_CLOCK_H __FILE__
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/**
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* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
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* @tcfg: The timer TCFG1 register bits shifted down to 0.
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*
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* Return true if the given configuration from TCFG1 is a TCLK instead
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* any of the TDIV clocks.
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*/
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static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
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{
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if (soc_is_s3c24xx())
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return tcfg == S3C2410_TCFG1_MUX_TCLK;
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else if (soc_is_s3c64xx() || soc_is_s5pc100())
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return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
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else if (soc_is_s5p6440() || soc_is_s5p6450())
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return 0;
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else
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return tcfg == S3C64XX_TCFG1_MUX_TCLK;
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}
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/**
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* tcfg_to_divisor() - convert tcfg1 setting to a divisor
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* @tcfg1: The tcfg1 setting, shifted down.
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*
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* Get the divisor value for the given tcfg1 setting. We assume the
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* caller has already checked to see if this is not a TCLK source.
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*/
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static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
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{
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if (soc_is_s3c24xx())
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return 1 << (tcfg1 + 1);
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else
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return 1 << tcfg1;
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}
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/**
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* pwm_tdiv_has_div1() - does the tdiv setting have a /1
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*
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* Return true if we have a /1 in the tdiv setting.
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*/
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static inline unsigned int pwm_tdiv_has_div1(void)
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{
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if (soc_is_s3c24xx())
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return 0;
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else
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return 1;
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}
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/**
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* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
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* @div: The divisor to calculate the bit information for.
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*
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* Turn a divisor into the necessary bit field for TCFG1.
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*/
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static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
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{
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if (soc_is_s3c24xx())
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return ilog2(div) - 1;
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else
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return ilog2(div);
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}
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#endif /* __ASM_PLAT_PWM_CLOCK_H */
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@ -1,474 +0,0 @@
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/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
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*
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* Copyright (c) 2007 Simtec Electronics
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* Copyright (c) 2007, 2008 Ben Dooks
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* Ben Dooks <ben-linux@fluff.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/log2.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <asm/irq.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/regs-timer.h>
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#include <plat/pwm-clock.h>
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/* Each of the timers 0 through 5 go through the following
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* clock tree, with the inputs depending on the timers.
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*
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* pclk ---- [ prescaler 0 ] -+---> timer 0
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* +---> timer 1
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*
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* pclk ---- [ prescaler 1 ] -+---> timer 2
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* +---> timer 3
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* \---> timer 4
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*
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* Which are fed into the timers as so:
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*
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* prescaled 0 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 0
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* tclk 0 ------------------------------/
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*
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* prescaled 0 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 1
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* tclk 0 ------------------------------/
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*
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*
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* prescaled 1 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 2
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* tclk 1 ------------------------------/
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*
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* prescaled 1 ---- [ div 2,4,8,16 ] ---\
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* [mux] -> timer 3
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* tclk 1 ------------------------------/
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*
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* prescaled 1 ---- [ div 2,4,8, 16 ] --\
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* [mux] -> timer 4
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* tclk 1 ------------------------------/
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*
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* Since the mux and the divider are tied together in the
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* same register space, it is impossible to set the parent
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* and the rate at the same time. To avoid this, we add an
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* intermediate 'prescaled-and-divided' clock to select
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* as the parent for the timer input clock called tdiv.
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*
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* prescaled clk --> pwm-tdiv ---\
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* [ mux ] --> timer X
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* tclk -------------------------/
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*/
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static struct clk clk_timer_scaler[];
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static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
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{
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unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
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if (clk == &clk_timer_scaler[1]) {
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tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
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tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
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} else {
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tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
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}
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return clk_get_rate(clk->parent) / (tcfg0 + 1);
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}
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static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long divisor = parent_rate / rate;
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if (divisor > 256)
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divisor = 256;
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else if (divisor < 2)
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divisor = 2;
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return parent_rate / divisor;
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}
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static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
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unsigned long tcfg0;
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unsigned long divisor;
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unsigned long flags;
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divisor = clk_get_rate(clk->parent) / round;
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divisor--;
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local_irq_save(flags);
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tcfg0 = __raw_readl(S3C2410_TCFG0);
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if (clk == &clk_timer_scaler[1]) {
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tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
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tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
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} else {
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tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
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tcfg0 |= divisor;
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}
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__raw_writel(tcfg0, S3C2410_TCFG0);
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local_irq_restore(flags);
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return 0;
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}
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static struct clk_ops clk_pwm_scaler_ops = {
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.get_rate = clk_pwm_scaler_get_rate,
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.set_rate = clk_pwm_scaler_set_rate,
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.round_rate = clk_pwm_scaler_round_rate,
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};
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static struct clk clk_timer_scaler[] = {
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[0] = {
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.name = "pwm-scaler0",
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.id = -1,
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.ops = &clk_pwm_scaler_ops,
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},
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[1] = {
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.name = "pwm-scaler1",
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.id = -1,
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.ops = &clk_pwm_scaler_ops,
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},
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};
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static struct clk clk_timer_tclk[] = {
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[0] = {
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.name = "pwm-tclk0",
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.id = -1,
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},
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[1] = {
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.name = "pwm-tclk1",
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.id = -1,
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},
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};
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struct pwm_tdiv_clk {
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struct clk clk;
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unsigned int divisor;
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};
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static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
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{
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return container_of(clk, struct pwm_tdiv_clk, clk);
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}
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static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
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{
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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unsigned int divisor;
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tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
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tcfg1 &= S3C2410_TCFG1_MUX_MASK;
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if (pwm_cfg_src_is_tclk(tcfg1))
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divisor = to_tdiv(clk)->divisor;
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else
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divisor = tcfg_to_divisor(tcfg1);
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return clk_get_rate(clk->parent) / divisor;
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}
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static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate;
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unsigned long divisor;
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parent_rate = clk_get_rate(clk->parent);
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divisor = parent_rate / rate;
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if (divisor <= 1 && pwm_tdiv_has_div1())
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divisor = 1;
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else if (divisor <= 2)
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divisor = 2;
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else if (divisor <= 4)
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divisor = 4;
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else if (divisor <= 8)
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divisor = 8;
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else
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divisor = 16;
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return parent_rate / divisor;
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}
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static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
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{
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return pwm_tdiv_div_bits(divclk->divisor);
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}
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static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
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{
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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unsigned long bits = clk_pwm_tdiv_bits(divclk);
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unsigned long flags;
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unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
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local_irq_save(flags);
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tcfg1 = __raw_readl(S3C2410_TCFG1);
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tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
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tcfg1 |= bits << shift;
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__raw_writel(tcfg1, S3C2410_TCFG1);
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local_irq_restore(flags);
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}
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static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
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{
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struct pwm_tdiv_clk *divclk = to_tdiv(clk);
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unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long divisor;
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tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
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tcfg1 &= S3C2410_TCFG1_MUX_MASK;
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rate = clk_round_rate(clk, rate);
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divisor = parent_rate / rate;
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if (divisor > 16)
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return -EINVAL;
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divclk->divisor = divisor;
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/* Update the current MUX settings if we are currently
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* selected as the clock source for this clock. */
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if (!pwm_cfg_src_is_tclk(tcfg1))
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clk_pwm_tdiv_update(divclk);
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return 0;
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}
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static struct clk_ops clk_tdiv_ops = {
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.get_rate = clk_pwm_tdiv_get_rate,
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.set_rate = clk_pwm_tdiv_set_rate,
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.round_rate = clk_pwm_tdiv_round_rate,
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};
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static struct pwm_tdiv_clk clk_timer_tdiv[] = {
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[0] = {
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.clk = {
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.name = "pwm-tdiv",
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.devname = "s3c24xx-pwm.0",
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.ops = &clk_tdiv_ops,
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.parent = &clk_timer_scaler[0],
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},
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},
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[1] = {
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.clk = {
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.name = "pwm-tdiv",
|
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.devname = "s3c24xx-pwm.1",
|
||||
.ops = &clk_tdiv_ops,
|
||||
.parent = &clk_timer_scaler[0],
|
||||
}
|
||||
},
|
||||
[2] = {
|
||||
.clk = {
|
||||
.name = "pwm-tdiv",
|
||||
.devname = "s3c24xx-pwm.2",
|
||||
.ops = &clk_tdiv_ops,
|
||||
.parent = &clk_timer_scaler[1],
|
||||
},
|
||||
},
|
||||
[3] = {
|
||||
.clk = {
|
||||
.name = "pwm-tdiv",
|
||||
.devname = "s3c24xx-pwm.3",
|
||||
.ops = &clk_tdiv_ops,
|
||||
.parent = &clk_timer_scaler[1],
|
||||
},
|
||||
},
|
||||
[4] = {
|
||||
.clk = {
|
||||
.name = "pwm-tdiv",
|
||||
.devname = "s3c24xx-pwm.4",
|
||||
.ops = &clk_tdiv_ops,
|
||||
.parent = &clk_timer_scaler[1],
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static int __init clk_pwm_tdiv_register(unsigned int id)
|
||||
{
|
||||
struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
|
||||
unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
|
||||
|
||||
tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
|
||||
tcfg1 &= S3C2410_TCFG1_MUX_MASK;
|
||||
|
||||
divclk->clk.id = id;
|
||||
divclk->divisor = tcfg_to_divisor(tcfg1);
|
||||
|
||||
return s3c24xx_register_clock(&divclk->clk);
|
||||
}
|
||||
|
||||
static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
|
||||
{
|
||||
return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
|
||||
}
|
||||
|
||||
static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
|
||||
{
|
||||
return &clk_timer_tdiv[id].clk;
|
||||
}
|
||||
|
||||
static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
unsigned int id = clk->id;
|
||||
unsigned long tcfg1;
|
||||
unsigned long flags;
|
||||
unsigned long bits;
|
||||
unsigned long shift = S3C2410_TCFG1_SHIFT(id);
|
||||
|
||||
unsigned long mux_tclk;
|
||||
|
||||
if (soc_is_s3c24xx())
|
||||
mux_tclk = S3C2410_TCFG1_MUX_TCLK;
|
||||
else if (soc_is_s5p6440() || soc_is_s5p6450())
|
||||
mux_tclk = 0;
|
||||
else
|
||||
mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
|
||||
|
||||
if (parent == s3c24xx_pwmclk_tclk(id))
|
||||
bits = mux_tclk << shift;
|
||||
else if (parent == s3c24xx_pwmclk_tdiv(id))
|
||||
bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
clk->parent = parent;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
tcfg1 = __raw_readl(S3C2410_TCFG1);
|
||||
tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
|
||||
__raw_writel(tcfg1 | bits, S3C2410_TCFG1);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops clk_tin_ops = {
|
||||
.set_parent = clk_pwm_tin_set_parent,
|
||||
};
|
||||
|
||||
static struct clk clk_tin[] = {
|
||||
[0] = {
|
||||
.name = "pwm-tin",
|
||||
.devname = "s3c24xx-pwm.0",
|
||||
.id = 0,
|
||||
.ops = &clk_tin_ops,
|
||||
},
|
||||
[1] = {
|
||||
.name = "pwm-tin",
|
||||
.devname = "s3c24xx-pwm.1",
|
||||
.id = 1,
|
||||
.ops = &clk_tin_ops,
|
||||
},
|
||||
[2] = {
|
||||
.name = "pwm-tin",
|
||||
.devname = "s3c24xx-pwm.2",
|
||||
.id = 2,
|
||||
.ops = &clk_tin_ops,
|
||||
},
|
||||
[3] = {
|
||||
.name = "pwm-tin",
|
||||
.devname = "s3c24xx-pwm.3",
|
||||
.id = 3,
|
||||
.ops = &clk_tin_ops,
|
||||
},
|
||||
[4] = {
|
||||
.name = "pwm-tin",
|
||||
.devname = "s3c24xx-pwm.4",
|
||||
.id = 4,
|
||||
.ops = &clk_tin_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static __init int clk_pwm_tin_register(struct clk *pwm)
|
||||
{
|
||||
unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
|
||||
unsigned int id = pwm->id;
|
||||
|
||||
struct clk *parent;
|
||||
int ret;
|
||||
|
||||
ret = s3c24xx_register_clock(pwm);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
|
||||
tcfg1 &= S3C2410_TCFG1_MUX_MASK;
|
||||
|
||||
if (pwm_cfg_src_is_tclk(tcfg1))
|
||||
parent = s3c24xx_pwmclk_tclk(id);
|
||||
else
|
||||
parent = s3c24xx_pwmclk_tdiv(id);
|
||||
|
||||
return clk_set_parent(pwm, parent);
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c_pwmclk_init() - initialise pwm clocks
|
||||
*
|
||||
* Initialise and register the clocks which provide the inputs for the
|
||||
* pwm timer blocks.
|
||||
*
|
||||
* Note, this call is required by the time core, so must be called after
|
||||
* the base clocks are added and before any of the initcalls are run.
|
||||
*/
|
||||
__init void s3c_pwmclk_init(void)
|
||||
{
|
||||
struct clk *clk_timers;
|
||||
unsigned int clk;
|
||||
int ret;
|
||||
|
||||
clk_timers = clk_get(NULL, "timers");
|
||||
if (IS_ERR(clk_timers)) {
|
||||
printk(KERN_ERR "%s: no parent clock\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
|
||||
clk_timer_scaler[clk].parent = clk_timers;
|
||||
|
||||
s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
|
||||
s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
|
||||
|
||||
for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
|
||||
ret = clk_pwm_tdiv_register(clk);
|
||||
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
|
||||
ret = clk_pwm_tin_register(&clk_tin[clk]);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user