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Documentation: x86: Remove cdpl2 unspported statement and fix capitalisation

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"L2 cache does not support code and data prioritization". This isn't
true, elsewhere the document says it can be enabled with the cdpl2
mount option.

While we're here, these sample strings have lower-case code/data,
which isn't how the kernel exports them.

Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
This commit is contained in:
James Morse 2019-06-07 16:14:07 +01:00 committed by Jonathan Corbet
parent eb8ed28f02
commit 7c7a499582
1 changed files with 10 additions and 4 deletions
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14
Documentation/x86/resctrl_ui.rst
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@ -418,16 +418,22 @@ L3 schemata file details (CDP enabled via mount option to resctrl)
When CDP is enabled L3 control is split into two separate resources
so you can specify independent masks for code and data like this::
L3data:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
L3code:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
L3DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
L3CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
L2 schemata file details
------------------------
L2 cache does not support code and data prioritization, so the
schemata format is always::
CDP is supported at L2 using the 'cdpl2' mount option. The schemata
format is either::
L2:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
or
L2DATA:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
L2CODE:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
Memory bandwidth Allocation (default mode)
------------------------------------------