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Merge branch 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

Browse Source 
* 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, mce: Use mce_sysdev_ prefix to group functions
  x86, mce: Use mce_chrdev_ prefix to group functions
  x86, mce: Cleanup mce_read()
  x86, mce: Cleanup mce_create()/remove_device()
  x86, mce: Check the result of ancient_init()
  x86, mce: Introduce mce_gather_info()
  x86, mce: Replace MCM_ with MCI_MISC_
  x86, mce: Replace MCE_SELF_VECTOR by irq_work
  x86, mce, severity: Clean up trivial coding style problems
  x86, mce, severity: Cleanup severity table
  x86, mce, severity: Make formatting a bit more readable
  x86, mce, severity: Fix two severities table signatures
This commit is contained in:
Linus Torvalds 2011-07-22 17:03:40 -07:00
commit 7c6582b28a
9 changed files with 250 additions and 235 deletions
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4
arch/x86/include/asm/entry_arch.h
View File

@ -53,8 +53,4 @@ BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR) BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)
#endif #endif
#ifdef CONFIG_X86_MCE
BUILD_INTERRUPT(mce_self_interrupt,MCE_SELF_VECTOR)
#endif
#endif #endif

1
arch/x86/include/asm/hw_irq.h
View File

@ -34,7 +34,6 @@ extern void irq_work_interrupt(void);
extern void spurious_interrupt(void); extern void spurious_interrupt(void);
extern void thermal_interrupt(void); extern void thermal_interrupt(void);
extern void reschedule_interrupt(void); extern void reschedule_interrupt(void);
extern void mce_self_interrupt(void);
extern void invalidate_interrupt(void); extern void invalidate_interrupt(void);
extern void invalidate_interrupt0(void); extern void invalidate_interrupt0(void);

5
arch/x86/include/asm/irq_vectors.h
View File

@ -109,11 +109,6 @@
#define UV_BAU_MESSAGE 0xf5 #define UV_BAU_MESSAGE 0xf5
/*
* Self IPI vector for machine checks
*/
#define MCE_SELF_VECTOR 0xf4
/* Xen vector callback to receive events in a HVM domain */ /* Xen vector callback to receive events in a HVM domain */
#define XEN_HVM_EVTCHN_CALLBACK 0xf3 #define XEN_HVM_EVTCHN_CALLBACK 0xf3

19
arch/x86/include/asm/mce.h
View File

@ -8,6 +8,7 @@
* Machine Check support for x86 * Machine Check support for x86
*/ */
/* MCG_CAP register defines */
#define MCG_BANKCNT_MASK 0xff /* Number of Banks */ #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
#define MCG_EXT_P (1ULL<<9) /* Extended registers available */ #define MCG_EXT_P (1ULL<<9) /* Extended registers available */
@ -17,10 +18,12 @@
#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
/* MCG_STATUS register defines */
#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
/* MCi_STATUS register defines */
#define MCI_STATUS_VAL (1ULL<<63) /* valid error */ #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
@ -31,12 +34,14 @@
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
#define MCI_STATUS_AR (1ULL<<55) /* Action required */ #define MCI_STATUS_AR (1ULL<<55) /* Action required */
/* MISC register defines */ /* MCi_MISC register defines */
#define MCM_ADDR_SEGOFF 0 /* segment offset */ #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
#define MCM_ADDR_LINEAR 1 /* linear address */ #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
#define MCM_ADDR_PHYS 2 /* physical address */ #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
#define MCM_ADDR_MEM 3 /* memory address */ #define MCI_MISC_ADDR_LINEAR 1 /* linear address */
#define MCM_ADDR_GENERIC 7 /* generic */ #define MCI_MISC_ADDR_PHYS 2 /* physical address */
#define MCI_MISC_ADDR_MEM 3 /* memory address */
#define MCI_MISC_ADDR_GENERIC 7 /* generic */
/* CTL2 register defines */ /* CTL2 register defines */
#define MCI_CTL2_CMCI_EN (1ULL << 30) #define MCI_CTL2_CMCI_EN (1ULL << 30)
@ -144,7 +149,7 @@ static inline void enable_p5_mce(void) {}
void mce_setup(struct mce *m); void mce_setup(struct mce *m);
void mce_log(struct mce *m); void mce_log(struct mce *m);
DECLARE_PER_CPU(struct sys_device, mce_dev); DECLARE_PER_CPU(struct sys_device, mce_sysdev);
/* /*
* Maximum banks number. * Maximum banks number.

150
arch/x86/kernel/cpu/mcheck/mce-severity.c
View File

@ -43,61 +43,105 @@ static struct severity {
unsigned char covered; unsigned char covered;
char *msg; char *msg;
} severities[] = { } severities[] = {
#define KERNEL .context = IN_KERNEL #define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
#define USER .context = IN_USER #define KERNEL .context = IN_KERNEL
#define SER .ser = SER_REQUIRED #define USER .context = IN_USER
#define NOSER .ser = NO_SER #define SER .ser = SER_REQUIRED
#define SEV(s) .sev = MCE_ ## s ## _SEVERITY #define NOSER .ser = NO_SER
#define BITCLR(x, s, m, r...) { .mask = x, .result = 0, SEV(s), .msg = m, ## r } #define BITCLR(x) .mask = x, .result = 0
#define BITSET(x, s, m, r...) { .mask = x, .result = x, SEV(s), .msg = m, ## r } #define BITSET(x) .mask = x, .result = x
#define MCGMASK(x, res, s, m, r...) \ #define MCGMASK(x, y) .mcgmask = x, .mcgres = y
{ .mcgmask = x, .mcgres = res, SEV(s), .msg = m, ## r } #define MASK(x, y) .mask = x, .result = y
#define MASK(x, y, s, m, r...) \
{ .mask = x, .result = y, SEV(s), .msg = m, ## r }
#define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S) #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
#define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR) #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
#define MCACOD 0xffff #define MCACOD 0xffff
BITCLR(MCI_STATUS_VAL, NO, "Invalid"), MCESEV(
BITCLR(MCI_STATUS_EN, NO, "Not enabled"), NO, "Invalid",
BITSET(MCI_STATUS_PCC, PANIC, "Processor context corrupt"), BITCLR(MCI_STATUS_VAL)
),
MCESEV(
NO, "Not enabled",
BITCLR(MCI_STATUS_EN)
),
MCESEV(
PANIC, "Processor context corrupt",
BITSET(MCI_STATUS_PCC)
),
/* When MCIP is not set something is very confused */ /* When MCIP is not set something is very confused */
MCGMASK(MCG_STATUS_MCIP, 0, PANIC, "MCIP not set in MCA handler"), MCESEV(
PANIC, "MCIP not set in MCA handler",
MCGMASK(MCG_STATUS_MCIP, 0)
),
/* Neither return not error IP -- no chance to recover -> PANIC */ /* Neither return not error IP -- no chance to recover -> PANIC */
MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0, PANIC, MCESEV(
"Neither restart nor error IP"), PANIC, "Neither restart nor error IP",
MCGMASK(MCG_STATUS_RIPV, 0, PANIC, "In kernel and no restart IP", MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
KERNEL), ),
BITCLR(MCI_STATUS_UC, KEEP, "Corrected error", NOSER), MCESEV(
MASK(MCI_STATUS_OVER|MCI_STATUS_UC|MCI_STATUS_EN, MCI_STATUS_UC, SOME, PANIC, "In kernel and no restart IP",
"Spurious not enabled", SER), KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
),
MCESEV(
KEEP, "Corrected error",
NOSER, BITCLR(MCI_STATUS_UC)
),
/* ignore OVER for UCNA */ /* ignore OVER for UCNA */
MASK(MCI_UC_SAR, MCI_STATUS_UC, KEEP, MCESEV(
"Uncorrected no action required", SER), KEEP, "Uncorrected no action required",
MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR, PANIC, SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
"Illegal combination (UCNA with AR=1)", SER), ),
MASK(MCI_STATUS_S, 0, KEEP, "Non signalled machine check", SER), MCESEV(
PANIC, "Illegal combination (UCNA with AR=1)",
SER,
MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
),
MCESEV(
KEEP, "Non signalled machine check",
SER, BITCLR(MCI_STATUS_S)
),
/* AR add known MCACODs here */ /* AR add known MCACODs here */
MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_SAR, PANIC, MCESEV(
"Action required with lost events", SER), PANIC, "Action required with lost events",
MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD, MCI_UC_SAR, PANIC, SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR)
"Action required; unknown MCACOD", SER), ),
MCESEV(
PANIC, "Action required: unknown MCACOD",
SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
),
/* known AO MCACODs: */ /* known AO MCACODs: */
MASK(MCI_UC_SAR|MCI_STATUS_OVER|0xfff0, MCI_UC_S|0xc0, AO, MCESEV(
"Action optional: memory scrubbing error", SER), AO, "Action optional: memory scrubbing error",
MASK(MCI_UC_SAR|MCI_STATUS_OVER|MCACOD, MCI_UC_S|0x17a, AO, SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|0xfff0, MCI_UC_S|0x00c0)
"Action optional: last level cache writeback error", SER), ),
MCESEV(
AO, "Action optional: last level cache writeback error",
SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCACOD, MCI_UC_S|0x017a)
),
MCESEV(
SOME, "Action optional: unknown MCACOD",
SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S)
),
MCESEV(
SOME, "Action optional with lost events",
SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S)
),
MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S, SOME, MCESEV(
"Action optional unknown MCACOD", SER), PANIC, "Overflowed uncorrected",
MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S|MCI_STATUS_OVER, SOME, BITSET(MCI_STATUS_OVER|MCI_STATUS_UC)
"Action optional with lost events", SER), ),
BITSET(MCI_STATUS_UC|MCI_STATUS_OVER, PANIC, "Overflowed uncorrected"), MCESEV(
BITSET(MCI_STATUS_UC, UC, "Uncorrected"), UC, "Uncorrected",
BITSET(0, SOME, "No match") /* always matches. keep at end */ BITSET(MCI_STATUS_UC)
),
MCESEV(
SOME, "No match",
BITSET(0)
) /* always matches. keep at end */
}; };
/* /*
@ -112,15 +156,15 @@ static int error_context(struct mce *m)
return IN_KERNEL; return IN_KERNEL;
} }
int mce_severity(struct mce *a, int tolerant, char **msg) int mce_severity(struct mce *m, int tolerant, char **msg)
{ {
enum context ctx = error_context(a); enum context ctx = error_context(m);
struct severity *s; struct severity *s;
for (s = severities;; s++) { for (s = severities;; s++) {
if ((a->status & s->mask) != s->result) if ((m->status & s->mask) != s->result)
continue; continue;
if ((a->mcgstatus & s->mcgmask) != s->mcgres) if ((m->mcgstatus & s->mcgmask) != s->mcgres)
continue; continue;
if (s->ser == SER_REQUIRED && !mce_ser) if (s->ser == SER_REQUIRED && !mce_ser)
continue; continue;
@ -197,15 +241,15 @@ static const struct file_operations severities_coverage_fops = {
static int __init severities_debugfs_init(void) static int __init severities_debugfs_init(void)
{ {
struct dentry *dmce = NULL, *fseverities_coverage = NULL; struct dentry *dmce, *fsev;
dmce = mce_get_debugfs_dir(); dmce = mce_get_debugfs_dir();
if (dmce == NULL) if (!dmce)
goto err_out; goto err_out;
fseverities_coverage = debugfs_create_file("severities-coverage",
0444, dmce, NULL, fsev = debugfs_create_file("severities-coverage", 0444, dmce, NULL,
&severities_coverage_fops); &severities_coverage_fops);
if (fseverities_coverage == NULL) if (!fsev)
goto err_out; goto err_out;
return 0; return 0;
@ -214,4 +258,4 @@ err_out:
return -ENOMEM; return -ENOMEM;
} }
late_initcall(severities_debugfs_init); late_initcall(severities_debugfs_init);
#endif #endif /* CONFIG_DEBUG_FS */

288
arch/x86/kernel/cpu/mcheck/mce.c
View File

@ -10,7 +10,6 @@
#include <linux/thread_info.h> #include <linux/thread_info.h>
#include <linux/capability.h> #include <linux/capability.h>
#include <linux/miscdevice.h> #include <linux/miscdevice.h>
#include <linux/interrupt.h>
#include <linux/ratelimit.h> #include <linux/ratelimit.h>
#include <linux/kallsyms.h> #include <linux/kallsyms.h>
#include <linux/rcupdate.h> #include <linux/rcupdate.h>
@ -38,23 +37,20 @@
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/edac_mce.h> #include <linux/edac_mce.h>
#include <linux/irq_work.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/idle.h>
#include <asm/ipi.h>
#include <asm/mce.h> #include <asm/mce.h>
#include <asm/msr.h> #include <asm/msr.h>
#include "mce-internal.h" #include "mce-internal.h"
static DEFINE_MUTEX(mce_read_mutex); static DEFINE_MUTEX(mce_chrdev_read_mutex);
#define rcu_dereference_check_mce(p) \ #define rcu_dereference_check_mce(p) \
rcu_dereference_index_check((p), \ rcu_dereference_index_check((p), \
rcu_read_lock_sched_held() || \ rcu_read_lock_sched_held() || \
lockdep_is_held(&mce_read_mutex)) lockdep_is_held(&mce_chrdev_read_mutex))
#define CREATE_TRACE_POINTS #define CREATE_TRACE_POINTS
#include <trace/events/mce.h> #include <trace/events/mce.h>
@ -94,7 +90,8 @@ static unsigned long mce_need_notify;
static char mce_helper[128]; static char mce_helper[128];
static char *mce_helper_argv[2] = { mce_helper, NULL }; static char *mce_helper_argv[2] = { mce_helper, NULL };
static DECLARE_WAIT_QUEUE_HEAD(mce_wait); static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
static DEFINE_PER_CPU(struct mce, mces_seen); static DEFINE_PER_CPU(struct mce, mces_seen);
static int cpu_missing; static int cpu_missing;
@ -372,6 +369,31 @@ static void mce_wrmsrl(u32 msr, u64 v)
wrmsrl(msr, v); wrmsrl(msr, v);
} }
/*
* Collect all global (w.r.t. this processor) status about this machine
* check into our "mce" struct so that we can use it later to assess
* the severity of the problem as we read per-bank specific details.
*/
static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
{
mce_setup(m);
m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
if (regs) {
/*
* Get the address of the instruction at the time of
* the machine check error.
*/
if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
m->ip = regs->ip;
m->cs = regs->cs;
}
/* Use accurate RIP reporting if available. */
if (rip_msr)
m->ip = mce_rdmsrl(rip_msr);
}
}
/* /*
* Simple lockless ring to communicate PFNs from the exception handler with the * Simple lockless ring to communicate PFNs from the exception handler with the
* process context work function. This is vastly simplified because there's * process context work function. This is vastly simplified because there's
@ -443,40 +465,13 @@ static void mce_schedule_work(void)
} }
} }
/* DEFINE_PER_CPU(struct irq_work, mce_irq_work);
* Get the address of the instruction at the time of the machine check
* error.
*/
static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
{
if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { static void mce_irq_work_cb(struct irq_work *entry)
m->ip = regs->ip;
m->cs = regs->cs;
} else {
m->ip = 0;
m->cs = 0;
}
if (rip_msr)
m->ip = mce_rdmsrl(rip_msr);
}
#ifdef CONFIG_X86_LOCAL_APIC
/*
* Called after interrupts have been reenabled again
* when a MCE happened during an interrupts off region
* in the kernel.
*/
asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
{ {
ack_APIC_irq();
exit_idle();
irq_enter();
mce_notify_irq(); mce_notify_irq();
mce_schedule_work(); mce_schedule_work();
irq_exit();
} }
#endif
static void mce_report_event(struct pt_regs *regs) static void mce_report_event(struct pt_regs *regs)
{ {
@ -492,29 +487,7 @@ static void mce_report_event(struct pt_regs *regs)
return; return;
} }
#ifdef CONFIG_X86_LOCAL_APIC irq_work_queue(&__get_cpu_var(mce_irq_work));
/*
* Without APIC do not notify. The event will be picked
* up eventually.
*/
if (!cpu_has_apic)
return;
/*
* When interrupts are disabled we cannot use
* kernel services safely. Trigger an self interrupt
* through the APIC to instead do the notification
* after interrupts are reenabled again.
*/
apic->send_IPI_self(MCE_SELF_VECTOR);
/*
* Wait for idle afterwards again so that we don't leave the
* APIC in a non idle state because the normal APIC writes
* cannot exclude us.
*/
apic_wait_icr_idle();
#endif
} }
DEFINE_PER_CPU(unsigned, mce_poll_count); DEFINE_PER_CPU(unsigned, mce_poll_count);
@ -541,9 +514,8 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
percpu_inc(mce_poll_count); percpu_inc(mce_poll_count);
mce_setup(&m); mce_gather_info(&m, NULL);
m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
for (i = 0; i < banks; i++) { for (i = 0; i < banks; i++) {
if (!mce_banks[i].ctl || !test_bit(i, *b)) if (!mce_banks[i].ctl || !test_bit(i, *b))
continue; continue;
@ -879,9 +851,9 @@ static int mce_usable_address(struct mce *m)
{ {
if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
return 0; return 0;
if ((m->misc & 0x3f) > PAGE_SHIFT) if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
return 0; return 0;
if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
return 0; return 0;
return 1; return 1;
} }
@ -942,9 +914,8 @@ void do_machine_check(struct pt_regs *regs, long error_code)
if (!banks) if (!banks)
goto out; goto out;
mce_setup(&m); mce_gather_info(&m, regs);
m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
final = &__get_cpu_var(mces_seen); final = &__get_cpu_var(mces_seen);
*final = m; *final = m;
@ -1028,7 +999,6 @@ void do_machine_check(struct pt_regs *regs, long error_code)
if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
mce_ring_add(m.addr >> PAGE_SHIFT); mce_ring_add(m.addr >> PAGE_SHIFT);
mce_get_rip(&m, regs);
mce_log(&m); mce_log(&m);
if (severity > worst) { if (severity > worst) {
@ -1190,7 +1160,8 @@ int mce_notify_irq(void)
clear_thread_flag(TIF_MCE_NOTIFY); clear_thread_flag(TIF_MCE_NOTIFY);
if (test_and_clear_bit(0, &mce_need_notify)) { if (test_and_clear_bit(0, &mce_need_notify)) {
wake_up_interruptible(&mce_wait); /* wake processes polling /dev/mcelog */
wake_up_interruptible(&mce_chrdev_wait);
/* /*
* There is no risk of missing notifications because * There is no risk of missing notifications because
@ -1363,18 +1334,23 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
return 0; return 0;
} }
static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
{ {
if (c->x86 != 5) if (c->x86 != 5)
return; return 0;
switch (c->x86_vendor) { switch (c->x86_vendor) {
case X86_VENDOR_INTEL: case X86_VENDOR_INTEL:
intel_p5_mcheck_init(c); intel_p5_mcheck_init(c);
return 1;
break; break;
case X86_VENDOR_CENTAUR: case X86_VENDOR_CENTAUR:
winchip_mcheck_init(c); winchip_mcheck_init(c);
return 1;
break; break;
} }
return 0;
} }
static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
@ -1428,7 +1404,8 @@ void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
if (mce_disabled) if (mce_disabled)
return; return;
__mcheck_cpu_ancient_init(c); if (__mcheck_cpu_ancient_init(c))
return;
if (!mce_available(c)) if (!mce_available(c))
return; return;
@ -1444,44 +1421,45 @@ void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
__mcheck_cpu_init_vendor(c); __mcheck_cpu_init_vendor(c);
__mcheck_cpu_init_timer(); __mcheck_cpu_init_timer();
INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
} }
/* /*
* Character device to read and clear the MCE log. * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
*/ */
static DEFINE_SPINLOCK(mce_state_lock); static DEFINE_SPINLOCK(mce_chrdev_state_lock);
static int open_count; /* #times opened */ static int mce_chrdev_open_count; /* #times opened */
static int open_exclu; /* already open exclusive? */ static int mce_chrdev_open_exclu; /* already open exclusive? */
static int mce_open(struct inode *inode, struct file *file) static int mce_chrdev_open(struct inode *inode, struct file *file)
{ {
spin_lock(&mce_state_lock); spin_lock(&mce_chrdev_state_lock);
if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { if (mce_chrdev_open_exclu ||
spin_unlock(&mce_state_lock); (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
spin_unlock(&mce_chrdev_state_lock);
return -EBUSY; return -EBUSY;
} }
if (file->f_flags & O_EXCL) if (file->f_flags & O_EXCL)
open_exclu = 1; mce_chrdev_open_exclu = 1;
open_count++; mce_chrdev_open_count++;
spin_unlock(&mce_state_lock); spin_unlock(&mce_chrdev_state_lock);
return nonseekable_open(inode, file); return nonseekable_open(inode, file);
} }
static int mce_release(struct inode *inode, struct file *file) static int mce_chrdev_release(struct inode *inode, struct file *file)
{ {
spin_lock(&mce_state_lock); spin_lock(&mce_chrdev_state_lock);
open_count--; mce_chrdev_open_count--;
open_exclu = 0; mce_chrdev_open_exclu = 0;
spin_unlock(&mce_state_lock); spin_unlock(&mce_chrdev_state_lock);
return 0; return 0;
} }
@ -1530,8 +1508,8 @@ static int __mce_read_apei(char __user **ubuf, size_t usize)
return 0; return 0;
} }
static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
loff_t *off) size_t usize, loff_t *off)
{ {
char __user *buf = ubuf; char __user *buf = ubuf;
unsigned long *cpu_tsc; unsigned long *cpu_tsc;
@ -1542,7 +1520,7 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
if (!cpu_tsc) if (!cpu_tsc)
return -ENOMEM; return -ENOMEM;
mutex_lock(&mce_read_mutex); mutex_lock(&mce_chrdev_read_mutex);
if (!mce_apei_read_done) { if (!mce_apei_read_done) {
err = __mce_read_apei(&buf, usize); err = __mce_read_apei(&buf, usize);
@ -1562,19 +1540,18 @@ static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
do { do {
for (i = prev; i < next; i++) { for (i = prev; i < next; i++) {
unsigned long start = jiffies; unsigned long start = jiffies;
struct mce *m = &mcelog.entry[i];
while (!mcelog.entry[i].finished) { while (!m->finished) {
if (time_after_eq(jiffies, start + 2)) { if (time_after_eq(jiffies, start + 2)) {
memset(mcelog.entry + i, 0, memset(m, 0, sizeof(*m));
sizeof(struct mce));
goto timeout; goto timeout;
} }
cpu_relax(); cpu_relax();
} }
smp_rmb(); smp_rmb();
err |= copy_to_user(buf, mcelog.entry + i, err |= copy_to_user(buf, m, sizeof(*m));
sizeof(struct mce)); buf += sizeof(*m);
buf += sizeof(struct mce);
timeout: timeout:
; ;
} }
@ -1594,13 +1571,13 @@ timeout:
on_each_cpu(collect_tscs, cpu_tsc, 1); on_each_cpu(collect_tscs, cpu_tsc, 1);
for (i = next; i < MCE_LOG_LEN; i++) { for (i = next; i < MCE_LOG_LEN; i++) {
if (mcelog.entry[i].finished && struct mce *m = &mcelog.entry[i];
mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
err |= copy_to_user(buf, mcelog.entry+i, if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
sizeof(struct mce)); err |= copy_to_user(buf, m, sizeof(*m));
smp_rmb(); smp_rmb();
buf += sizeof(struct mce); buf += sizeof(*m);
memset(&mcelog.entry[i], 0, sizeof(struct mce)); memset(m, 0, sizeof(*m));
} }
} }
@ -1608,15 +1585,15 @@ timeout:
err = -EFAULT; err = -EFAULT;
out: out:
mutex_unlock(&mce_read_mutex); mutex_unlock(&mce_chrdev_read_mutex);
kfree(cpu_tsc); kfree(cpu_tsc);
return err ? err : buf - ubuf; return err ? err : buf - ubuf;
} }
static unsigned int mce_poll(struct file *file, poll_table *wait) static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
{ {
poll_wait(file, &mce_wait, wait); poll_wait(file, &mce_chrdev_wait, wait);
if (rcu_access_index(mcelog.next)) if (rcu_access_index(mcelog.next))
return POLLIN | POLLRDNORM; return POLLIN | POLLRDNORM;
if (!mce_apei_read_done && apei_check_mce()) if (!mce_apei_read_done && apei_check_mce())
@ -1624,7 +1601,8 @@ static unsigned int mce_poll(struct file *file, poll_table *wait)
return 0; return 0;
} }
static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
unsigned long arg)
{ {
int __user *p = (int __user *)arg; int __user *p = (int __user *)arg;
@ -1652,16 +1630,16 @@ static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
/* Modified in mce-inject.c, so not static or const */ /* Modified in mce-inject.c, so not static or const */
struct file_operations mce_chrdev_ops = { struct file_operations mce_chrdev_ops = {
.open = mce_open, .open = mce_chrdev_open,
.release = mce_release, .release = mce_chrdev_release,
.read = mce_read, .read = mce_chrdev_read,
.poll = mce_poll, .poll = mce_chrdev_poll,
.unlocked_ioctl = mce_ioctl, .unlocked_ioctl = mce_chrdev_ioctl,
.llseek = no_llseek, .llseek = no_llseek,
}; };
EXPORT_SYMBOL_GPL(mce_chrdev_ops); EXPORT_SYMBOL_GPL(mce_chrdev_ops);
static struct miscdevice mce_log_device = { static struct miscdevice mce_chrdev_device = {
MISC_MCELOG_MINOR, MISC_MCELOG_MINOR,
"mcelog", "mcelog",
&mce_chrdev_ops, &mce_chrdev_ops,
@ -1719,7 +1697,7 @@ int __init mcheck_init(void)
} }
/* /*
* Sysfs support * mce_syscore: PM support
*/ */
/* /*
@ -1739,12 +1717,12 @@ static int mce_disable_error_reporting(void)
return 0; return 0;
} }
static int mce_suspend(void) static int mce_syscore_suspend(void)
{ {
return mce_disable_error_reporting(); return mce_disable_error_reporting();
} }
static void mce_shutdown(void) static void mce_syscore_shutdown(void)
{ {
mce_disable_error_reporting(); mce_disable_error_reporting();
} }
@ -1754,18 +1732,22 @@ static void mce_shutdown(void)
* Only one CPU is active at this time, the others get re-added later using * Only one CPU is active at this time, the others get re-added later using
* CPU hotplug: * CPU hotplug:
*/ */
static void mce_resume(void) static void mce_syscore_resume(void)
{ {
__mcheck_cpu_init_generic(); __mcheck_cpu_init_generic();
__mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
} }
static struct syscore_ops mce_syscore_ops = { static struct syscore_ops mce_syscore_ops = {
.suspend = mce_suspend, .suspend = mce_syscore_suspend,
.shutdown = mce_shutdown, .shutdown = mce_syscore_shutdown,
.resume = mce_resume, .resume = mce_syscore_resume,
}; };
/*
* mce_sysdev: Sysfs support
*/
static void mce_cpu_restart(void *data) static void mce_cpu_restart(void *data)
{ {
del_timer_sync(&__get_cpu_var(mce_timer)); del_timer_sync(&__get_cpu_var(mce_timer));
@ -1801,11 +1783,11 @@ static void mce_enable_ce(void *all)
__mcheck_cpu_init_timer(); __mcheck_cpu_init_timer();
} }
static struct sysdev_class mce_sysclass = { static struct sysdev_class mce_sysdev_class = {
.name = "machinecheck", .name = "machinecheck",
}; };
DEFINE_PER_CPU(struct sys_device, mce_dev); DEFINE_PER_CPU(struct sys_device, mce_sysdev);
__cpuinitdata __cpuinitdata
void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
@ -1934,7 +1916,7 @@ static struct sysdev_ext_attribute attr_cmci_disabled = {
&mce_cmci_disabled &mce_cmci_disabled
}; };
static struct sysdev_attribute *mce_attrs[] = { static struct sysdev_attribute *mce_sysdev_attrs[] = {
&attr_tolerant.attr, &attr_tolerant.attr,
&attr_check_interval.attr, &attr_check_interval.attr,
&attr_trigger, &attr_trigger,
@ -1945,66 +1927,67 @@ static struct sysdev_attribute *mce_attrs[] = {
NULL NULL
}; };
static cpumask_var_t mce_dev_initialized; static cpumask_var_t mce_sysdev_initialized;
/* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
static __cpuinit int mce_create_device(unsigned int cpu) static __cpuinit int mce_sysdev_create(unsigned int cpu)
{ {
struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
int err; int err;
int i, j; int i, j;
if (!mce_available(&boot_cpu_data)) if (!mce_available(&boot_cpu_data))
return -EIO; return -EIO;
memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); memset(&sysdev->kobj, 0, sizeof(struct kobject));
per_cpu(mce_dev, cpu).id = cpu; sysdev->id = cpu;
per_cpu(mce_dev, cpu).cls = &mce_sysclass; sysdev->cls = &mce_sysdev_class;
err = sysdev_register(&per_cpu(mce_dev, cpu)); err = sysdev_register(sysdev);
if (err) if (err)
return err; return err;
for (i = 0; mce_attrs[i]; i++) { for (i = 0; mce_sysdev_attrs[i]; i++) {
err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
if (err) if (err)
goto error; goto error;
} }
for (j = 0; j < banks; j++) { for (j = 0; j < banks; j++) {
err = sysdev_create_file(&per_cpu(mce_dev, cpu), err = sysdev_create_file(sysdev, &mce_banks[j].attr);
&mce_banks[j].attr);
if (err) if (err)
goto error2; goto error2;
} }
cpumask_set_cpu(cpu, mce_dev_initialized); cpumask_set_cpu(cpu, mce_sysdev_initialized);
return 0; return 0;
error2: error2:
while (--j >= 0) while (--j >= 0)
sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); sysdev_remove_file(sysdev, &mce_banks[j].attr);
error: error:
while (--i >= 0) while (--i >= 0)
sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
sysdev_unregister(&per_cpu(mce_dev, cpu)); sysdev_unregister(sysdev);
return err; return err;
} }
static __cpuinit void mce_remove_device(unsigned int cpu) static __cpuinit void mce_sysdev_remove(unsigned int cpu)
{ {
struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
int i; int i;
if (!cpumask_test_cpu(cpu, mce_dev_initialized)) if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
return; return;
for (i = 0; mce_attrs[i]; i++) for (i = 0; mce_sysdev_attrs[i]; i++)
sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
for (i = 0; i < banks; i++) for (i = 0; i < banks; i++)
sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); sysdev_remove_file(sysdev, &mce_banks[i].attr);
sysdev_unregister(&per_cpu(mce_dev, cpu)); sysdev_unregister(sysdev);
cpumask_clear_cpu(cpu, mce_dev_initialized); cpumask_clear_cpu(cpu, mce_sysdev_initialized);
} }
/* Make sure there are no machine checks on offlined CPUs. */ /* Make sure there are no machine checks on offlined CPUs. */
@ -2054,7 +2037,7 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
switch (action) { switch (action) {
case CPU_ONLINE: case CPU_ONLINE:
case CPU_ONLINE_FROZEN: case CPU_ONLINE_FROZEN:
mce_create_device(cpu); mce_sysdev_create(cpu);
if (threshold_cpu_callback) if (threshold_cpu_callback)
threshold_cpu_callback(action, cpu); threshold_cpu_callback(action, cpu);
break; break;
@ -2062,7 +2045,7 @@ mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
case CPU_DEAD_FROZEN: case CPU_DEAD_FROZEN:
if (threshold_cpu_callback) if (threshold_cpu_callback)
threshold_cpu_callback(action, cpu); threshold_cpu_callback(action, cpu);
mce_remove_device(cpu); mce_sysdev_remove(cpu);
break; break;
case CPU_DOWN_PREPARE: case CPU_DOWN_PREPARE:
case CPU_DOWN_PREPARE_FROZEN: case CPU_DOWN_PREPARE_FROZEN:
@ -2116,27 +2099,28 @@ static __init int mcheck_init_device(void)
if (!mce_available(&boot_cpu_data)) if (!mce_available(&boot_cpu_data))
return -EIO; return -EIO;
zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
mce_init_banks(); mce_init_banks();
err = sysdev_class_register(&mce_sysclass); err = sysdev_class_register(&mce_sysdev_class);
if (err) if (err)
return err; return err;
for_each_online_cpu(i) { for_each_online_cpu(i) {
err = mce_create_device(i); err = mce_sysdev_create(i);
if (err) if (err)
return err; return err;
} }
register_syscore_ops(&mce_syscore_ops); register_syscore_ops(&mce_syscore_ops);
register_hotcpu_notifier(&mce_cpu_notifier); register_hotcpu_notifier(&mce_cpu_notifier);
misc_register(&mce_log_device);
/* register character device /dev/mcelog */
misc_register(&mce_chrdev_device);
return err; return err;
} }
device_initcall(mcheck_init_device); device_initcall(mcheck_init_device);
/* /*

10
arch/x86/kernel/cpu/mcheck/mce_amd.c
View File

@ -548,7 +548,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
if (!b) if (!b)
goto out; goto out;
err = sysfs_create_link(&per_cpu(mce_dev, cpu).kobj, err = sysfs_create_link(&per_cpu(mce_sysdev, cpu).kobj,
b->kobj, name); b->kobj, name);
if (err) if (err)
goto out; goto out;
@ -571,7 +571,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
goto out; goto out;
} }
b->kobj = kobject_create_and_add(name, &per_cpu(mce_dev, cpu).kobj); b->kobj = kobject_create_and_add(name, &per_cpu(mce_sysdev, cpu).kobj);
if (!b->kobj) if (!b->kobj)
goto out_free; goto out_free;
@ -591,7 +591,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
if (i == cpu) if (i == cpu)
continue; continue;
err = sysfs_create_link(&per_cpu(mce_dev, i).kobj, err = sysfs_create_link(&per_cpu(mce_sysdev, i).kobj,
b->kobj, name); b->kobj, name);
if (err) if (err)
goto out; goto out;
@ -669,7 +669,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
/* sibling symlink */ /* sibling symlink */
if (shared_bank[bank] && b->blocks->cpu != cpu) { if (shared_bank[bank] && b->blocks->cpu != cpu) {
sysfs_remove_link(&per_cpu(mce_dev, cpu).kobj, name); sysfs_remove_link(&per_cpu(mce_sysdev, cpu).kobj, name);
per_cpu(threshold_banks, cpu)[bank] = NULL; per_cpu(threshold_banks, cpu)[bank] = NULL;
return; return;
@ -681,7 +681,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
if (i == cpu) if (i == cpu)
continue; continue;
sysfs_remove_link(&per_cpu(mce_dev, i).kobj, name); sysfs_remove_link(&per_cpu(mce_sysdev, i).kobj, name);
per_cpu(threshold_banks, i)[bank] = NULL; per_cpu(threshold_banks, i)[bank] = NULL;
} }

5
arch/x86/kernel/entry_64.S
View File

@ -984,11 +984,6 @@ apicinterrupt THRESHOLD_APIC_VECTOR \
apicinterrupt THERMAL_APIC_VECTOR \ apicinterrupt THERMAL_APIC_VECTOR \
thermal_interrupt smp_thermal_interrupt thermal_interrupt smp_thermal_interrupt
#ifdef CONFIG_X86_MCE
apicinterrupt MCE_SELF_VECTOR \
mce_self_interrupt smp_mce_self_interrupt
#endif
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
apicinterrupt CALL_FUNCTION_SINGLE_VECTOR \ apicinterrupt CALL_FUNCTION_SINGLE_VECTOR \
call_function_single_interrupt smp_call_function_single_interrupt call_function_single_interrupt smp_call_function_single_interrupt

3
arch/x86/kernel/irqinit.c
View File

@ -272,9 +272,6 @@ static void __init apic_intr_init(void)
#ifdef CONFIG_X86_MCE_THRESHOLD #ifdef CONFIG_X86_MCE_THRESHOLD
alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt); alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
#endif #endif
#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
#endif
#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
/* self generated IPI for local APIC timer */ /* self generated IPI for local APIC timer */